
MOTOROLA
Chapter 7. Reset
7-7
Reset Configuration
7.5
Reset Configuration
7.5.1
Hard Reset Configuration
When a hard reset event occurs, the MPC565/MPC566 reconfigures its hardware system as
well as the development port configuration. The logical value of the bits that determine its
initial mode of operation, are sampled from the following:
The external data bus pins DATA[0:31]
An internal default constant (0x0000 0000)
An internal NVM register value (UC3FCFIG)
If at the sampling time RSTCONF is asserted, then the configuration is sampled from the
data bus. If RSTCONF is negated and a valid NVM value exists (UC3FCFIG bit HC=0),
then the configuration is sampled from the NVM register in the UC3F module. If
RSTCONF is negated and no valid NVM value exists (UC3FCFIG bit HC=1), then the
configuration word is sampled from the internal default. HC will be “1” if the internal flash
is erased.
Table 7-4 summarizes the reset configuration options.
If the PRDS control bit in the PDMCR register is set and HRESET and RSTCONF are
asserted, the MPC565/MPC566 pulls the data bus low with a weak resistor. The user can
11
GHRST
Glitch detected on HRESET pin. This bit is set when the HRESET pin is asserted for more than
20ns
0 No glitch was detected on the HRESET pin
1 A glitch was detected on the HRESET pin
12
GSRST
Glitch detected on SRESET pin. If the SRESET pin is asserted for more than 20ns the GHRST
bit will be set. If an internal or external SRESET is generated the SRESET pinisassertedand
the GSRST bit will be set. The GSRST bit remains set until software clears it. The GSRST bit can
be negated by writing a one to GSRST. A write of zero has no effect on this bit.
0 No glitch was detected on SRESET pin
1 A glitch was detected on SRESET pin
.
13:15
—
Reserved
1 In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal. The EHRS and ESRS bits in RSR
register are set for any internal reset source in addition to external HRESET and external SRESET events. If both
internal and external indicator bits are set, then the reset source is internal.
Table 7-4. Reset Configuration Options
RSTCONF
Has Configuration (HC)
Internal Configuration Word
0
x
DATA[0:31] pins
1
0
NVM flash EEPROM register (UC3FCFIG)
1
Internal data word default (0x0000 0000)
Table 7-3. Reset Status Register Bit Descriptions (continued)
Bit(s)
Name
Description