
MOTOROLA
Chapter 13. Queued Analog-To-Digital Converter (QADC64E)
13-5
Features, Overview and Quick Reference Diagrams
Each QADC on MPC565/MPC566 has its own memory location.
Table 13-1 shows the
memory map for QADC64E module A. Module B has the same offset scheme starting at
QADC64E_A occupies 0x30 4800 to 0x30 4BFF
QADC64E_B occupies 0x30 4C00 to 0x30 4FFF
Table 13-1. QADC64E_A Address Map
Address
MSB
LSB
Register
0123456789
10
11
12
13
14
15
0x30 4800
ST
O
P
FR
Z
--
SUPV
MS
T
R
EXT
CLK
--
Module
Config.
0x30 4802
TEST MODE
---
Test
0x30 4804
IRL1
IRL2
--
Interrupt
0x30 4806
PORTQA
PORTQB
Port Data
0x30 4808
DDRQA
DDRQB
Port
Direction
0x30 480A
EM
UX
---
TRIG
--
QCLK PRESCALER
Control 0
0x30 480C
CI
E1
PI
E1
SSE1
MQ1
---
Control 1
0x30 480E
CIE2
PIE2
SSE2
MQ2
RESU.
BQ2
Control 2
0x30 4810
CF1
PF1
CF2
PF2
TO
R
1
TO
R
2
QS
CWP
Status 0
0x30 4812
--
CWPQ1
---
CWPQ2
Status 1
0x30 4814-
0x30 49FF
--14 Words Reserved --
Reserved
0x30 4A00-
0x30 4A7F
--
P
REF
IST
CHAN
CCWs
0x30 4A80-
0x30 4AFF
0000 00
UNSIGNED RIGHT JUSTIFIED
Results
0x30 4B00-
0x30 4B7F
SI
G
N
SIGNED LEFT JUSTIFIED
00 0000
Results
0x30 4B80
0x30 4BFF
UNSIGNED LEFT JUSTIFIED
00 0000
Results
Note: Registers in Bold are accessible only as supervisor data space