
MOTOROLA
Chapter 3. Central Processing Unit
3-53
Operating Environment Architecture (OEA)
The enhanced interrupt controller mode is available for interrupt-driven applications on
MPC565/MPC566. It allows the single external interrupt exception vector 0x500 to be split
into up to 48 different vectors corresponding to 48 interrupt sources in order to speed up
interrupt processing. It also supports low priority source masking feature in hardware to
When an external interrupt is taken, instruction execution resumes at offset 0x00500 from
the physical base address indicated by MSR[IP].
3.15.4.6 Alignment Exception (0x00600)
The following conditions cause an alignment exception:
The operand of a floating-point load or store instruction is not word-aligned.
The operand of a load or store multiple instruction is not word-aligned.
The operand of lwarx or stwcx. is not word-aligned.
Alignment exceptions use the SRR0 and SRR1 to save the machine state and the DSISR to
determine the source of the exception.
The register settings for alignment exceptions are shown in
Table 3-29.Table 3-28. Register Settings Following External Interrupt
Register
Bits
Setting Description
Save/Restore Register 0 (SRR0) 1
1 If the exception occurs during a data access in “Decompression On” mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format. If the exception occurs during an instruction fetch in
“Decompression On” mode, the SRR0 register will contain an indeterminate value.
All
Set to the effective address of the instruction that the processor
would have attempted to execute next if no interrupt conditions
were present.
Save/Restore Register 1 (SRR1)
[0:15]
Cleared to 0
[16:31]
Loaded from bits [16:31] of MSR. In the current implementation,
bit 30 of the SRR1 is never cleared, except by loading a zero
value from MSR[RI]
Machine State Register (MSR)
IP
No change
ME
No change
LE
Set to value of ILE bit prior to the exception
DCMPEN
This bit is set according to
(BBCMCR[EN_COMP] & BBCMCR[EXC_COMP])
Other
Clearedto0