
2-18
MPC565/MPC566 Reference Manual
MOTOROLA
Signal Descriptions
2.4.1.43 ENGCLK / BUCLK
Pin Name: engclk_buclk
ENGCLK – This is the engineering clock output. Drive voltage can be configured to 2.6 V,
5 V (with slew-rate control) or disabled. The drive voltage is configured using the
EECLK[0:1] bits in the SCCR register in the SIU.
BUCLK – When the chip is in limp mode, it is operating from a less precise on-chip ring
oscillator to allow the system to continue minimum functionality until the system clock is
fixed. This backup clock can be seen externally if selected by the values of the EECLK[0:1]
bits in the SCCR register in the USIU.
2.4.1.44 PULL_SEL
Pin Name: pull_sel
Pull Select – This pin determines whether the pull devices on the MIOS and TPU pins are
pull-ups or pull-downs. When pull-ups are selected, the pull-ups are to 5.0 V. The following
MIOS pins always have pull down resistors unless disabled in the PDMCR register:
VF[0:2]/MPIO32B[0:2], VFLS[0:1]/MPIO32B[3:4], and MDO[7:4]/MPIO32B[7:10].
2.4.2
QSMCM A / QSMCM B / DLCMD2 (J1850) Pads
The MPC565/MPC566 has two QSMCM modules, QSMCM A and QSMCM B.
QSMCM A has identical function to the MPC555/MPC556’s QSMCM A module.
QSMCM B has its RXD2 and PCS[3] pins muxed with the DLCMD2 (J1850) module. The
muxing of the pins is controlled by the QPAPCS3 bit in the QSMCM_B pin assignment
register (PQSPAR), according to
Table 2-5. The muxed pins default to the DLCMD2
function at reset. Because the normal function of the PCS pins within the QSMCM require
that this bit be written before the PCS pin is used, the muxing appears transparent to both
the QSMCM B and the DLCMD2 modules. However, only one of the modules, DLCMD2
or QSMCM B can use the pins in a system. Because of this muxed function on QSMCM
B, the general-purpose input and output functions are not available on the B_PCS[3] and
B_RXD2 pins
Table 2-5. DLCMD2 / QSMCM B SCI2 Pin Mux Control
QPAPCS3 Bit Value
QSMCM_B / DLCMD2 Pin Function
0
B_PCS[3] / J1850_TX pin assigned to J1850_TX.
B_RXD2 / J1850_RX pin assigned to J1850_RX.
Pins are assigned to DLCMD2 (J1850_TX and J1850_RX)
1
B_PCS[3] / J1850_TX pin assigned to PCS[3].
B_RXD2 / J1850_RX pin assigned to B_RXD2.
Pins are assigned to QSMCM B SCI2 (B_PCS[3] and B_RXD2)