
MOTOROLA
Appendix E. Electrical Characteristics
E-11
DC Electrical Characteristics
7 Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each
eight to 12 °C, in the ambient temperature range of 50 to 125 °C.
8 All bus pins support two drive strengths capabilities, 25 pF and 50 pF. Current drive is less at the 25-pF
capacitive load. Both modes achieve 40-MHz (or, optionally, 56-MHz) timing.
9 Only IRQ, TPU, MIOS, GPIO, QADC (when digital inputs) and RESET pins have hysteresis, thus there is no hysteresis
specification on all other pins
10 All power consumption specifications assume 50-pF loads and running a typical application. Of the power consumption
of some modules could go up is they are exercised heavier, but the power consumption of other modules would
decrease.
11 Current measured at maximum system clock frequency with QADC active.
12 Transient currents can reach 50mA.
13 KAPWR and V
DDSRAM can be powered-up prior to any other supply or at the same time as the other 2.6 V supplies.
14 This parameter is periodically sampled rather than 100% tested
15 Up to 0.5 V during power up/down.
16
17 To obtain full-range results, V
SSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA
18 The voltage at which the LVSRS bits in the VSRAMCR register will be set ranges from TBD to TBD volts. V
STBY should
remain above TBD volts to prevent LVSRS bits to be set.
19 This parameter is guaranteed by design.
20 All injection current is transferred to the V
DDH. An external load is required to dissipate this current to maintain the
power supply within the specified voltage range.
21 Total injection current for all I/O pins on the chip must not exceed 20 mA (sustained current). Exceeding this limit can
cause disruption of normal operation.
22 Current refers to two QADC64 modules operating simultaneously.
23 Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs
greater than VRH and 0x000 for values less than VRL. This assumes that VRH ≤ VDDA and VRL ≥ VSSA due to the
presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.