
7-2
MPC565/MPC566 Reference Manual
MOTOROLA
Reset Operation
frequency, PLL multiplication factor, and the PITRTCLK and TMBCLK clock sources. In
addition, the MPC565/MPC566 asserts the SRESET and HRESET pins.
The PORESET pin should be asserted for a minimum time of 100,000 cycles of clock
oscillator after a valid level has been reached on the KAPWR supply. After detecting the
assertion of PORESET, the MPC565/MPC566 remains in the power-on reset state until the
last of the following two events occurs:
The Internal PLL enters the lock state and the system clock is active.
The PORESET pin is negated.
If the MPC565/MPC566 is in single-chip mode and limp mode is enabled, the internal PLL
is not required to be locked before the chip exits power-on reset.
After exiting the power-on reset state, the MCU continues to drive the HRESET and
SRESET pins for 512 system clock cycles. When the timer expires (after 512 cycles), the
Configuration”) and the MCU stops driving the HRESET and SRESET pins. In addition,
the internal MODCK[1:3] values are sampled at the rising edge of PORESET.
The PORESET pin has a glitch detector to ensure that low spikes of less than 20 ns are
rejected. The internal PORESET signal asserts only if the PORESET pin asserts for more
than 100 ns.
7.1.2
Hard Reset
HRESET (hard reset) is an active low, bidirectional I/O pin. The MPC565/MPC566 can
detect an external assertion of HRESET only if it occurs while the MCU is not asserting
HRESET.
When the MPC565/MPC566 detects assertion of the external HRESET pin or a cause to
assert the internal HRESET line, is detected the chip starts to drive the HRESET and
SRESET for 512 cycles. When the timer expires (after 512 cycles) the configuration is
stops driving the HRESET and SRESET pins. An external pull-up resistor should drive the
HRESET and SRESET pins high. After detecting the negation of HRESET or SRESET,the
MCU waits 16 clock cycles before testing the presence of an external hard or soft reset.
The HRESET pin has a glitch detector to ensure that low spikes of less than 20 ns are
rejected. The internal HRESET will be asserted only if HRESET is asserted for more than
100 ns.
The HRESET is an open collector type pin.