參數(shù)資料
型號： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 97/116頁
文件大?。?/td> 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
97 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
13.4.4
SPI timing
Table 161. SPI timing specification
Symbol
Parameter
t
SCKL
SCK LOW time
t
SCKH
SCK HIGH time
t
DSHQX
data output hold after data strobe
HIGH time
t
DQXCH
data input/output changing to clock
HIGH time
t
h(SCKL-Q)
SCK LOW to data output hold time
t
(SCKL-NSSH)
SCK LOW to NSS HIGH time
Remark:
To send more bytes in one data stream the NSS signal must be LOW during the
send process. To send more than one data stream the NSS signal must be HIGH between
each data stream.
13.4.5
Clock frequency
The clock input is pin OSCIN.
Table 162. Clock frequency
Symbol
Parameter
f
clk
clock frequency
The clock applied to the MFRC531 acts as a time constant for the synchronous system’s
encoder and decoder. The stability of the clock frequency is an important factor for
ensuring proper performance. To obtain highest performance, clock jitter must be as small
as possible. This is best achieved using the internal oscillator buffer and the
recommended circuitry; see
Section 9.8 on page 29
.
Conditions
Min
100
100
20
Typ
-
-
-
Max Unit
-
-
-
ns
ns
ns
20
-
-
ns
-
20
-
-
15
-
ns
ns
Fig 23. Timing diagram for SPI
001aaj641
t
SCKL
t
SCKH
t
SCKL
t
DQXCH
t
DSHQX
t
DQXCH
t
h(SCKL-Q)
t
CLSH
SCK
MOSI
MISO
MSB
MSB
LSB
LSB
NSS
Conditions
checked by the clock
filter
Min
-
Typ
13.56
Max
-
Unit
MHz
δ
clk
t
jit
clock duty cycle
jitter time
40
-
50
-
60
10
%
ps
of clock edges
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