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| 型號(hào)： | MFRC53101T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ISO-IEC 14443 reader IC |
| 封裝： | MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html< |
| 文件頁(yè)數(shù)： | 34/116頁(yè) |
| 文件大?。?/td> | 862K |
| 代理商： | MFRC53101T |
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MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
34 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
Automatic calibration can be set-up to execute at the end of each Transceive command if
bit ClkQCalib = logic 0. Setting bit ClkQCalib = logic 1 disables all automatic calibrations
except after the reset sequence. Automatic calibration can also be triggered by the
software when bit ClkQCalib has a logic 0 to logic 1 transition.
Remark:
The duration of the automatic Q-clock calibration is 65 oscillator periods or
approximately 4.8
μ
s.
The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift
between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the
phase-shift between the Q-clock and the I-clock is greater than 180
°
.
Remark:
The StartUp configuration file enables automatic Q-clock calibration after a reset
If bit ClkQCalib = logic 1, automatic calibration is not performed. Leaving this bit set to
logic 1 can be used to permanently disable automatic calibration.
It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The
aim could be to disable automatic calibration and set the delay using the software.
Configuring the delay value using the software requires bit ClkQCalib to have been
previously set to logic 1 and a time interval of at least 4.8
μ
s has elapsed. Each delay
value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the
configured delay value is overwritten by the next automatic calibration interval.
9.10.2.2
Amplifier
The demodulated signal must be amplified by the variable amplifier to achieve the best
performance. The gain of the amplifiers can be adjusted using the RxControl1 register
Gain[1:0] bits; see
Table 27
.
Table 27.
See
Table 83 “RxControl1 register bit descriptions” on page 61
for additional information.
Register setting
Fig 12. Automatic Q-clock calibration
001aak616
calibration impulse
from reset sequence
a rising edge initiates
Q-clock calibration
ClkQCalib bit
calibration impulse
from end of
Transceive command
Gain factors for the internal amplifier
Gain factor [dB]
(simulation results)
20
24
31
35
00
01
10
11
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