參數(shù)資料
型號: MFRC53101T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡(luò)
英文描述: ISO-IEC 14443 reader IC
封裝: MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù): 23/116頁
文件大?。?/td> 862K
代理商: MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
23 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
9.5.1
Timer unit implementation
9.5.1.1
Timer unit block diagram
Figure 8
shows the block diagram of the timer module.
The timer unit is designed, so that events when combined with enabling flags start or stop
the counter. For example, setting bit TStartTxBegin = logic 1 enables control of received
data with the timer unit. In addition, the first received bit is indicated by the TxBegin event.
This combination starts the counter at the defined TReloadValue[7:0].
The timer stops automatically when the counter value is equal to zero or if a defined stop
event happens.
9.5.1.2
Controlling the timer unit
The main part of the timer unit is a down-counter. As long as the down-counter value is
not zero, it decrements its value with each timer clock cycle.
If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On
reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0].
Fig 8.
Timer module block diagram
001aak611
TxEnd Event
TAutoRestart
TRunning
TStartTxEnd
TStartNow
S
R
Q
START COUNTER/
PARALLEL LOAD
STOP COUNTER
TPreScaler[4:0]
TimerValue[7:0]
Counter = 0
to interrupt logic: TimerIRq
PARALLEL OUT
PARALLEL IN
TReloadValue[7:0]
CLOCK
DIVIDER
COUNTER MODULE
(x
x
1)
TStopNow
TxBegin Event
TStartTxBegin
TStopRxEnd
RxEnd Event
TStopRxBegin
13.56 MHz
to parallel interface
RxBegin Event
Q
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