參數(shù)資料
型號(hào)： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 6/116頁
文件大?。?/td> 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
6 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
[1]
Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.
[2]
The SLRC400 uses pin name SIGOUT for pin MFOUT. The MFRC531 functionality includes test functions for the SLRC400 using pin
MFOUT.
[3]
These pins provide different functionality depending on the selected microprocessor interface type (see
Section 9.1 on page 7
for
detailed information).
13
13 to 20
[3]
D0
D0 to D7
AD0 to AD7
ALE
AS
nAStrb
NSS
A0
nWait
O
I/O
I/O
I
I
I
I
I
O
SPI master in, slave out output
8-bit bidirectional data bus input/output on pins D0 to D7
8-bit bidirectional address and data bus input/output on pins AD0 to AD7
address latch enable input for pins AD0 to AD5; HIGH latches the internal address
address strobe input for pins AD0 to AD5; HIGH latches the internal address
not address strobe input for pins AD0 to AD5; LOW latches the internal address
not slave select strobe input for SPI communication
address line 0 is the address register bit 0 input
not wait output:
LOW starts an access cycle
HIGH ends an access cycle
SPI master out, slave in
address line 1 is the address register bit 1 input
address line 2 is the address register bit 2 input
SPI serial clock input
digital power supply
analog power supply for pins OSCIN, OSCOUT, RX, VMID and AUX
auxiliary output is used to generate analog test signals. The output signal is
selected using the TestAnaSelect register’s TestAnaOutSel[4:0] bits
21
[3]
22
[3]
MOSI
A1
A2
SCK
DVDD
AVDD
AUX
I
I
I
I
P
P
O
23
24
[3]
25
26
27
28
29
AVSS
RX
G
I
analog ground
receiver input: used as the card response input. The carrier is load modulated at
13.56 MHz, drawn from the antenna circuit
internal reference voltage pin provides the internal reference voltage as a supply
Remark:
It must be connected to a 100 nF block capacitor connected between pin
VMID and ground
reset and power-down input:
HIGH: the internal current sinks are switched off, the oscillator is inhibited and
the input pads are disconnected
LOW (negative edge): start internal reset phase
crystal oscillator output for the oscillator’s inverting amplifier
30
VMID
P
31
RSTPD
I
32
OSCOUT
O
Table 3.
Pin
Pin description
…continued
Symbol
Type
[1]
Description
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