參數(shù)資料
型號： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網絡
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 41/116頁
文件大?。?/td> 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
41 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
9.14.2
Authentication procedure
The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid
authentication, the correct key has to be available in the key buffer of the MFRC531. This
can be ensured as follows:
1. Load the internal key buffer by using the LoadKeyE2 (see
Section 11.6.1 on page 88
)
or the LoadKey (see
Section 11.6.2 on page 88
) commands.
2. Start the Authent1 command (see
Section 11.6.3 on page 89
). When finished, check
the error flags to obtain the command execution status.
3. Start the Authent2 command (see
Section 11.6.4 on page 89
). When finished, check
the error flags and bit Crypto1On to obtain the command execution status.
10. MFRC531 registers
10.1 Register addressing modes
Three methods can be used to operate the MFRC531:
initiating functions and controlling data by executing commands
configuring the functional operation using a set of configuration bits
monitoring the state of the MFRC531 by reading status flags
The commands, configuration bits and flags are accessed using the microprocessor
interface. The MFRC531 can internally address 64 registers using six address lines.
10.1.1
Page registers
The MFRC531 register set is segmented into eight pages contain eight registers each. A
Page register can always be addressed, irrespective of which page is currently selected.
10.1.2
Dedicated address bus
When using the MFRC531 with the dedicated address bus, the microprocessor defines
three address lines using address pins A0, A1 and A2. This enables addressing within a
page. To switch between registers in different pages a paging mechanism needs to be
used.
Table 34
shows how the register address is assembled.
Table 34.
Register bit: UsePageSelect
1
10.1.3
Multiplexed address bus
The microprocessor may define all six address lines at once using the MFRC531 with a
multiplexed address bus. In this case, either the paging mechanism or linear addressing
can be used.
Table 35
shows how the register address is assembled.
Dedicated address bus: assembling the register address
Register address
PageSelect2
PageSelect1
PageSelect0
A2
A1
A0
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