參數(shù)資料
型號： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 20/116頁
文件大小： 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
20 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
Table 19.
Interrupt flag
TimerIRq
TxIRq
9.4.2
Interrupt request handling
9.4.2.1
Controlling interrupts and getting their status
The MFRC531 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
If any interrupt request flag is set to logic 1 (showing that an interrupt request is pending)
and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is
set to logic 1. Different interrupt sources can activate simultaneously because all interrupt
request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ.
9.4.2.2
Accessing the interrupt registers
The interrupt request bits are automatically set by the MFRC531’s internal state
machines. In addition, the microprocessor can also set or clear the interrupt request bits
as required.
A special implementation of the InterruptRq and InterruptEn registers enables changing
an individual bit status without influencing any other bits. If an interrupt register is set to
logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. If a
specific interrupt flag is cleared, zero must be written to the SetIxx and the interrupt
register address must be set to logic 1 at the same time.
If a content bit is not changed during the setting or clearing phase, zero must be written to
the specific bit location.
Example:
Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0
while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq
to logic 1 and leaves all other bits unchanged.
Interrupt sources
Interrupt source
timer unit
transmitter
CRC coprocessor
EEPROM
Trigger action
timer counts from 1 to 0
a data stream, transmitted to the card, ends
all data from the FIFO buffer has been processed
all data from the FIFO buffer has been
programmed
a data stream, received from the card, ends
command execution finishes
FIFO buffer is full
FIFO buffer is empty
RxIRq
IdleIRq
HiAlertIRq
LoAlertIRq
receiver
Command register
FIFO buffer
FIFO buffer
Table 20.
Register
InterruptEn
InterruptRq
Interrupt control registers
Bit 7
SetIEn
SetIRq
Bit 6
reserved
reserved
Bit 5
TimerIEn
TimerIRq
Bit 4
TxIEn
TxIRq
Bit 3
RxIEn
RxIRq
Bit 2
IdleIEn
IdleIRq
Bit 1
HiAlertIEn
HiAlertIRq
Bit 0
LoAlertIEn
LoAlertIRq
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