參數(shù)資料
型號: MFRC53101T
廠商: NXP Semiconductors N.V.
元件分類: 通信及網(wǎng)絡
英文描述: ISO-IEC 14443 reader IC
封裝: MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù): 70/116頁
文件大?。?/td> 862K
代理商: MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
70 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
10.5.6.6
IRQPinConfig register
Configures the output stage for pin IRQ.
Table 116. IRQPinConfig register (address: 2Dh) reset value: 0000 0010b, 02h bit allocation
Bit
7
6
5
4
Symbol
000000
Access
R/W
Table 117. IRQPinConfig register bit descriptions
Bit
Symbol
7 to 2
000000
1
IRQInv
10.5.6.7
PreSet2E register
Table 118. PreSet2E register (address: 2Eh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
Symbol
x
x
x
Access
W
W
W
10.5.6.8
PreSet2F register
Table 119. PreSet2F register (address: 2Fh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
Symbol
x
x
x
Access
W
W
W
10.5.7
Page 6: reserved
10.5.7.1
Page register
Selects the page register; see
Section 10.5.1.1 “Page register” on page 48
.
10.5.7.2
Reserved registers 31h, 32h, 33h, 34h, 35h, 36h and 37h
Table 120. Reserved registers (address: 31h, 32h, 33h, 34h, 35h, 36h, 37h)
reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
Symbol
x
x
x
Access
R/W
R/W
R/W
Remark:
These registers are reserved for future use.
3
2
1
0
IRQInv
R/W
IRQPushPull
R/W
Value
-
1
0
1
0
Description
these values must not be changed
inverts the signal on pin IRQ with respect to bit IRq
the signal on pin IRQ is not inverted and is the same as bit IRq
pin IRQ functions as a standard CMOS output pad
pin IRQ functions as an open-drain output pad
0
IRQPushPull
4
x
W
3
x
W
2
x
W
1
x
W
0
x
W
4
x
W
3
x
W
2
x
W
1
x
W
0
x
W
4
x
3
x
2
x
1
x
0
x
R/W
R/W
R/W
R/W
R/W
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