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| 型號(hào)： | MFRC53101T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ISO-IEC 14443 reader IC |
| 封裝： | MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html< |
| 文件頁(yè)數(shù)： | 62/116頁(yè) |
| 文件大小： | 862K |
| 代理商： | MFRC53101T |
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MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
62 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
10.5.4.3
DecoderControl register
Controls decoder operation.
Table 84.
Table 85.
Bit
7
6
10.5.4.4
BitPhase register
Selects the bit-phase between transmitter and receiver clock.
Table 86.
Bit
Symbol
Access
Table 87.
Bit
7 to 0
DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit
allocation
7
6
5
0
RxMultiple ZeroAfterColl
RxFraming[1:0]
R/W
R/W
R/W
Bit
Symbol
Access
4
3
2
1
0
00
R/W
RxCoding
R/W
R/W
DecoderControl register bit descriptions
Symbol
Value
0
-
RxMultiple
0
1
ZeroAfterColl
1
Description
this value must not be changed
after receiving one frame, the receiver is deactivated
enables reception of more than one frame
any bits received after a bit-collision are masked to zero. This
helps to resolve the anti-collision procedure as defined in
ISO/IEC 14443 A
MIFARE or ISO/IEC 14443 A
this value must not be changed
Manchester encoding
BPSK encoding
5
4 to 3 RxFraming[1:0]
2 to 1 00
0
RxCoding
01
-
0
1
BitPhase register (address: 1Bh) reset value: 1010 1101b, ADh bit allocation
7
6
5
4
BitPhase[7:0]
3
2
1
0
R/W
BitPhase register bit descriptions
Symbol
Description
BitPhase
defines the phase relationship between transmitter and receiver clock
Remark:
The correct value of this register is essential for proper
operation.
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