參數(shù)資料
型號： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 87/116頁
文件大?。?/td> 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
87 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
11.4.1.2
Relevant LoadConfig command error flags
Valid EEPROM starting byte addresses are between 10h and 60h.
Copying from block 8h to 1Fh (keys) is restricted. Reading from these addresses sets the
flag AccessErr = logic 1.
Addresses above 1FFh are taken as modulo 200h; see
Section 9.2 on page 12
for the
EEPROM memory organization.
11.4.2
CalcCRC command 12h
Table 142. CalcCRC command 12h
Command
Value
The CalcCRC command takes all the data from the FIFO buffer as the input bytes for the
CRC coprocessor. All data stored in the FIFO buffer before the command is started is
processed.
This command does not return any data to the FIFO buffer but the content of the CRC can
be read using the CRCResultLSB and CRCResultMSB registers.
The CalcCRC command can only be started by the microprocessor and it does not
automatically stop. It must be stopped by the microprocessor sending the Idle command.
If the FIFO buffer is empty, the CalcCRC command waits for further input before
proceeding.
11.4.2.1
CRC coprocessor settings
Table 143
shows the parameters that can be configured for the CRC coprocessor.
Table 143. CRC coprocessor parameters
Parameter
Value
CRC register
length
CRC algorithm
ISO/IEC 14443 A or ISO/IEC 3309
CRC preset value
any
The CRC polynomial for the 8-bit CRC is fixed to x
8
+ x
4
+ x
3
+ x
2
+ 1.
The CRC polynomial for the 16-bit CRC is fixed to x
16
+ x
12
+ x
5
+ 1.
11.4.2.2
CRC coprocessor status flags
The CRCReady status flag indicates that the CRC coprocessor has finished processing
all the data bytes in the FIFO buffer. When the CRCReady flag is set to logic 1, an
interrupt is requested which sets the TxIRq flag. This supports interrupt driven use of the
CRC coprocessor.
When CRCReady and TxIRq flags are set to logic 1 the content of the CRCResultLSB
and CRCResultMSB registers and the CRCErr flag are valid. The CRCResultLSB and
CRCResultMSB registers hold the content of the CRC, the CRCErr flag indicates CRC
validity for the processed data.
Action
Arguments and
data
data byte stream
Returned data
CalcCRC
12h
activates the CRC coprocessor
-
Bit
CRC8
Register
ChannelRedundancy
8-bit or 16-bit CRC
CRC3309
CRCPresetLSB
CRCPresetMSB CRCPresetMSB
ChannelRedundancy
CRCPresetLSB
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