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參數(shù)資料
| 型號： | MFRC53101T |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | ISO-IEC 14443 reader IC |
| 封裝： | MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html< |
| 文件頁數(shù)： | 78/116頁 |
| 文件大?。?/td> | 862K |
| 代理商： | MFRC53101T |
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MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
78 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
As long as the internal accept further data signal is logic 1, further data can be written to
the FIFO buffer. The MFRC531 appends this data to the data stream transmitted using the
RF interface.
If the internal accept further data signal is logic 0, the transmission terminates. All data
written to the FIFO buffer after accept further data signal was set to logic 0 is not
transmitted, however, it remains in the FIFO buffer.
Remark:
If parity generation is enabled (ParityEn = logic 1), the parity bit is the last bit
transmitted. This delays the accept further data signal by a duration of one bit.
If the TxLastBits[2:0] bits are not zero, the last byte is not transmitted completely. Only the
number of bits set by TxLastBits[2:0], starting with the least significant bit are transmitted.
This means that the internal state machine has to check the FIFO buffer status at an
earlier point in time; see
Figure 17
.
Since in this example TxLastBits[2:0] = 4, transmission stops after bit 3 is transmitted and
the frame is completed with an EOF, if configured.
Fig 16. Timing for transmitting byte oriented frames
Fig 17. Timing for transmitting bit oriented frames
001aak619
accept further data
check FIFO empty
TxData
FIFO empty
FIFOLength[6:0]
0x01
0x00
TxLastBits[2:0]
TxLastBits = 0
7
0
7
7
0
001aak620
accept further data
check FIFO empty
TxData
FIFO empty
FIFOLength[6:0]
0x01
0x00
0x01
0x00
TxLastBits[2:0]
TxLastBits = 4
NWR (FIFO data)
7
0
3
4
7
0
3
4
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