參數(shù)資料
型號(hào)： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 51/116頁
文件大?。?/td> 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
51 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
10.5.1.6
SecondaryStatus register
Various secondary status flags.
Table 49.
Table 50.
Bit
7
10.5.1.7
InterruptEn register
Control bits to enable and disable passing of interrupt requests.
Table 51.
Bit
Symbol
Access
Table 52.
Bit
7
[1]
This bit can only be set or cleared using bit SetIEn.
SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit
allocation
7
6
5
TRunning
E2Ready
CRCReady
R
R
R
Bit
Symbol
Access
4
3
2
1
0
00
R
RxLastBits[2:0]
R
SecondaryStatus register bit descriptions
Symbol
Value
TRunning
1
Description
the timer unit is running and the counter decrements the
TimerValue register on the next timer clock cycle
the timer unit is not running
EEPROM programming is finished
EEPROM programming is ongoing
CRC calculation is finished
CRC calculation is ongoing
reserved
shows the number of valid bits in the last received byte. If zero,
the whole byte is valid
0
1
0
1
0
-
-
6
E2Ready
5
CRCReady
4 to 3 00
2 to 0 RxLastBits[2:0]
InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
7
6
5
4
SetIEn
0
TimerIEn
TxIEn
W
R/W
R/W
R/W
3
2
1
0
RxIEn
R/W
IdleIEn
R/W
HiAlertIEn
R/W
LoAlertIEn
R/W
InterruptEn register bit descriptions
Symbol
Value
Description
SetIEn
1
indicates that the marked bits in the InterruptEn register are set
0
clears the marked bits
0
-
reserved
TimerIEn
-
sends the TimerIRq timer interrupt request to pin IRQ
[1]
TxIEn
-
sends the TxIRq transmitter interrupt request to pin IRQ
[1]
RxIEn
-
sends the RxIRq receiver interrupt request to pin IRQ
[1]
IdleIEn
-
sends the IdleIRq idle interrupt request to pin IRQ
[1]
HiAlertIEn
-
sends the HiAlertIRq high alert interrupt request to pin IRQ
[1]
LoAlertIEn -
sends the LoAlertIRq low alert interrupt request to pin IRQ
[1]
6
5
4
3
2
1
0
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