參數(shù)資料
型號(hào)： MC68HC55CD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16
封裝： SOIC-16
文件頁(yè)數(shù)： 7/40頁(yè)
文件大?。?/td> 284K
代理商： MC68HC55CD
MC68HC55 Technical Data
DSI Channel Control Registers
MC68HC55
Technical Data
Registers and Bit Descriptions
15
This register should be written before data is sent over the DSI bus.
Any write to this register causes any DSI transfer in progress on this
DSI channel to be aborted (see 4.2 Abort Function). The bits in this
register are updated as they are received over the SPI interface, but
no new values take effect until the next DSI clock cycle after the
conclusion of the SPI write to this register.
CDIV1[B:A] — Clock Divider for Channel 1 Bits
The CDIV1[B:A] bits specify an additional divider between the SCLK
input and the bit timing circuitry. When CDIV1[B:A] are set for 0:0,
each bit time on the DSI/D to DSI/P interface is three SCLK periods
long.
DLY1[B:A] — Inter-Frame Delay for Channel 1 Bits
These bits specify the minimum delay between transfer frames on the
DSI/D to DSI/P interface. When DLY1[B:A] are set for 0:0, there will
be a minimum of four bit times of idle line from the end of a transfer
Address:
$110
Bit 7
654321
Bit 0
Read:
CDIV1B
CDIV1A
DLY1B
DLY1A
RIE1
TIE1
0
MS1
Write:
Reset:
00000000
Figure 3-7. DSI Channel 1 Control Register (DSI1CTRL)
Table 3-4. CDIV1 Divider Information
CDIV1[B:A]
Divisor
SCLK Periods
per Bit Time
0:0
÷13
0:1
÷26
1:0
÷412
1:1
÷824
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