參數(shù)資料
型號(hào): MC68HC55CD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16
封裝: SOIC-16
文件頁(yè)數(shù): 39/40頁(yè)
文件大?。?/td> 284K
代理商: MC68HC55CD
MC68HC55 Technical Data
Technical Data
MC68HC55
8
Registers and Bit Descriptions
line. A logic 0 starts with a falling edge on DSI0S and is low for two-thirds
of the bit time and then high for one-third of the bit time. A logic 1 starts
with a falling edge on DSI0S and is low for one-third of the bit time and
then high for two-thirds of the bit time.
DSI0F
— DSI channel 0 frame. This output idles high and is driven low
during each transfer frame.
VDD — This is the positive voltage supply input (nom. 5 V).
Section 3. Registers and Bit Descriptions
The MC68HC55 includes eight 8-bit registers. A master MCU reads from
or writes to these registers through an SPI. For more information about
the SPI and command protocol, refer to 4.4 SPI Communications
Table 3-1. Register Summary
Register
Address
Register
Name
Description
000
DSI0H
DSI channel 0 data register (upper byte)
001
DSI0L
DSI channel 0 data register (lower byte)
010
DSI1H
DSI channel 1 data register (upper byte)
011
DSI1L
DSI channel 1 data register (lower byte)
100
DSISTAT
DSI status register
101
DSI0CTRL
DSI channel 0 control register
110
DSI1CTRL
DSI channel 1 control register
111
DSIENABLE
DSI channel enable bits
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