參數(shù)資料
型號(hào)： MC68HC55CD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16
封裝： SOIC-16
文件頁(yè)數(shù)： 13/40頁(yè)
文件大?。?/td> 284K
代理商： MC68HC55CD
MC68HC55 Technical Data
Technical Data
MC68HC55
20
Functional Description
4.2 Abort Function
Any DSI transfer that was in progress is stopped as soon as the SPI write
that caused the abort begins. The DSI/D to DSI/P interface lines return
to their idle states. The abort condition is true throughout the SPI write
to the DSI control register.
After the last bit of the DSI control register is written, the transmit and
receive FIFO pointers are reset, which effectively clears these FIFOs
and forces the FIFO locations to 0. A minimum inter-frame delay is then
timed (using the new values of clock scaling and delay control bits) to
allow reserve capacitors in remote nodes to charge. (Any partial
inter-frame delay based on old control settings is forgotten.)
4.3 Enable (Disable) Function
When a DSI channel is disabled, its DSIxF pin is high and its DSIxS pin
is low which forces the DSI/P device to three-state its bus output. The
transmit and receive FIFO pointers are reset, which effectively clears
these FIFOs and forces the FIFO locations to 0. Any DSI transfer that
was in progress is stopped.
Although the SPI clock and the DSI input clock both typically come from
the same MCU system clock in an MCU plus DSI/D system, there is no
guaranteed relationship between these clocks, so the system was
designed as if these clocks were asynchronous. The FIFO architecture
eliminated most of the cases where these clocks need to interact, and
the remaining cases were designed with extra care to prevent
asynchronous problems.
explains the notation used in the subsequent state diagrams.
Entry to the IDLE state is asynchronous and all other state transitions
are synchronous. The note in the upper right corner of the figure
identifies which edge of which clock or signal is used to synchronize
state transitions. Each arrow or arc has a condition which must be true
before the transition can take place. This condition can be the value of a
single signal or a more complex logic function. A slash (/) indicates the
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