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參數(shù)資料
| 型號(hào)： | MC68HC55CD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 284K |
| 代理商： | MC68HC55CD |
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MC68HC55 Technical Data
Timing Characteristics for DSI/D to DSI/P Interface
MC68HC55
Technical Data
Timing and Electrical Specifications
35
Figure 5-1. DSI/D to DSI/P Interface Timing
Parameter(1)
Symbol
Min
Typ
Max
Units
Communication rate (MC68HC55 to DSI/P)
—
5
—
150
kbits/s
Signal bit time (tSCLKCYC * 3, 6, 12, or 24)
tBit
6.67
—
200
s
Master clock cycle time
tSCLKCYC
2.22
tBit/3
66.7
s
Master clock duty cycle
—
40
50
60
%
Frame start to signal delay time
tDLY1
tBit–0.2
tBit
tBit+0.2
s
Signal end to frame end delay time
tDLY2
–0.2
0
0.2
s
Signal low time for logic 0
(33.3% duty cycle guaranteed by design)
t0LO
2/3tBit–0.2 2/3tBit 2/3tBit+0.2
s
Signal low time for logic 1
(66.7% duty cycle guaranteed by design)
t1LO
1/3tBit–0.2 1/3tBit 1/3tBit+0.2
s
Receive data setup — DSI1R, DSI0R
tRSU
20
—
ns
Receive data hold — DSI1R, DSI0R
tRH
20
—
ns
Rise time (20% VDD to 70% VDD)
DSI1F, DSI1S, DSI0F, DSI0S
tRise
—
100
ns
Fall time (70% VDD to 20% VDD)
DSI1F, DSI1S, DSI0F, DSI0S
tFall
—
100
ns
1. 4.5 volts
≤ VDD ≤ 5.5 volts; –40°C ≤ TAMB ≤ 85°C; C ≤ 100 pF load on all DSI/D to DSI/P pins
DSIxF
DSIxS
DSIxR
tBit
t1LO
t0LO
tDLY2
tDLY1
tFall
tRise
tRH
tRSU
LOGIC 0 BIT TIME
LOGIC 1 BIT TIME
LAST CRC BIT TIME
tBit
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