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參數(shù)資料
| 型號： | MC68HC55CD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 15/40頁 |
| 文件大?。?/td> | 284K |
| 代理商： | MC68HC55CD |
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MC68HC55 Technical Data
Technical Data
MC68HC55
22
Functional Description
Figure 4-3. State Diagram — SPI Transfer
In the SPI_BURST state, new SPI characters are read-from or
written-to-and-read-from DSI/D registers. If the control register is written,
an ABORT request is generated which will immediately stop any DSI
transfer that was in progress (refer to Figure 4-4). If the DATA register
low byte is written, a transmit FIFO push operation is generated (see
). If the DATA register low byte is accessed (read or written)
and there is at least one entry in the receive FIFO, a receive FIFO pop
operation is generated.
When a DSI transfer results in both an R_FIFO_PUSH and an
X_FIFO_POP, the R_FIFO_PUSH is performed first to avoid the
possibility of the transmit FIFO from getting ahead of the receive FIFO.
describes what happens during DSI serial transfers. State
transfers in this state machine are synchronous with positive edges on
the scaled SCLK and the initial state is WAIT_FRAME_DELAY. Initial
entry into this state is caused by a reset, abort, or by enable becoming
inactive. These conditions cause an asynchronous entry into this state.
The exit to the next state, TRANSFER_DSI_BITS, needs to be
synchronous.
SPI_IDLE
SPI_COMMAND_XFER
SPI_BURST
RESET or CS_INACTIVE/
SPI_WRITE = 0
SPI_BIT_PTR = 7
CS_ACTIVE/
SPI_WRITE = DATA_IN
~LAST_SPI_BIT/
SPI_BIT_PTR = SPI_BIT_PTR – 1
LAST_SPI_BIT/
IF SPI_WRITE & REG_PTR = DATA_L THEN X_FIFO PUSH
REG_PTR = REG_PTR+1 (rolls over 7-0)
IF SPI_WRITE & REG_PTR = CTRL THEN ABORT
LAST_SPI_BIT/
SPI_BIT_PTR = 7;
INITIALIZE REG_PTR FROM COMMAND BITS 2-0
~LAST_SPI_BIT/
SPI_BIT_PTR = SPI_BIT_PTR – 1
SPI_BIT_PTR = 7
IF R_FIFO_NOT_EMPTY & REG_PTR = DATA_L THEN R_FIFO_POP
STATE MACHINE TRANSITIONS
ON RISING EDGES OF SPI CLOCK
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