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參數(shù)資料
| 型號： | MC68HC55CD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 3/40頁 |
| 文件大?。?/td> | 284K |
| 代理商： | MC68HC55CD |
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MC68HC55 Technical Data
DSI Status Register
MC68HC55
Technical Data
Registers and Bit Descriptions
11
visible via the SPI until chip select rises and returns low to start a new
SPI transfer. Reads of this register should be considered a snapshot of
the status at the last falling edge of chip select.
NOTE:
To guarantee coherence between an SPI read of status and data, the
reads must be within the same SPI burst (CS must remain continuously
low for the data and status reads). One way to assure this is to always
read data in a burst, starting with a command referencing DSI0H through
DSI1L, leaving the register pointer pointing at the DSISTAT register (see
Figure 4-7). The first SPI transfer which corresponds to the read or write
address 000 command will return (read) register 100 (DSISTAT). The
values of DSISTAT and DSI0H through DSI1L are latched at the falling
edge of CS, so changes due to DSI transfers are not seen until a future
SPI transfer.
ER1 — CRC Error Bit (Channel 1 Read)
0 = CRC value for the data in the read buffer was correct.
1 = CRC value for the data in the read buffer was not correct (data
is not valid).
CRC errors are associated with each data value in the receive FIFO,
so each FIFO entry has a bit to indicate whether the data in that stage
of the FIFO was received correctly.
Whenever a received value is visible at DSI1H:DSI1L, the associated
CRC error status is visible at ER1 in the DSISTAT register. When a
new data value becomes visible due to a pop of a previous value, the
ER1 status flag reflects the CRC status of the new data value. There
is no separate interrupt associated with ER1 because it is always
associated with the RFNE1 status flag.
TFE1 — Transmit FIFO Empty Bit (Channel 1)
0 = Transmit FIFO not empty
1 = Transmit FIFO empty
When the transmit FIFO is empty, four consecutive write bursts may
be used to fill the FIFO without checking the flags between writes. An
interrupt may be generated on the transmit FIFO empty condition.
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