參數(shù)資料
型號: MC68HC55CD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16
封裝: SOIC-16
文件頁數(shù): 11/40頁
文件大?。?/td> 284K
代理商: MC68HC55CD
MC68HC55 Technical Data
Reset Function
MC68HC55
Technical Data
Functional Description
19
Figure 4-1. MC68HC55 Block Diagram
4.1 Reset Function
A low level on RESET forces all FIFO bits to be cleared. The receive and
transmit FIFO pointers are cleared, which effectively forces the FIFOs to
the empty condition. Since the DSI channels are disabled (ENx = 0), the
DSIxF pins are high and the DSIxS pins are low, which forces the DSI/P
devices to three-state their bus outputs.
Reset also forces all MC68HC55 state machines to their idle state.
DSI0F
DSI0S
CLK
DI
DO
CS
SCLK
CHANNEL
0
MC68HC55 — DISTRIBUTED SYSTEM INTERFACE — DIGITAL PORTION
INT
RESET
Rx FIFO
Tx FIFO
DSI0
SPI
SPI_XFER
DATA
ER
DATA
ER
DATA
ER
DATA
ER
DATA
Rx FIFO
Tx FIFO
DATA
ER
DATA
ER
DATA
ER
DATA
ER
DATA
INTERRUPT
STATUS REG
CONTROL REGS
REG POINTER
BIT POINTER
CRC GENERATION
CRC CHECKING
MUX
16
DATA
DSI_XFER_0
PUSH
POP
MUX
16
DATA
ER0
ER1
1
DATA
1
DATA
PUSH
POP
ENABLE REG
POP
PUSH
ENx
ABORT
SPI_LAST_BIT
CLOCK DIVIDERS
DSI1F
DSI1S
CHANNEL
1
DSI1R
DSI1
CRC GENERATION
CRC CHECKING
MUX
16
DATA
DSI_XFER_1
PUSH
POP
DIV BY 1, 2, 4, or 8
SCALED SCLKs
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