參數(shù)資料
型號(hào)： MC68HC55CD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16
封裝： SOIC-16
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 284K
代理商： MC68HC55CD
MC68HC55 Technical Data
Technical Data
MC68HC55
28
Functional Description
sent from the master MCU (MOSI) to the DSI/D (DI) is captured on rising
edges of SCK and written, bit by bit, to the selected register as data bits
are received (X_FIFO is not pushed unless all bits of DATA_L written).
At the end of the transfer, the internal DSI/D register pointer is
incremented (rolls over to 000 if it was 111 during this transfer).
The current data from the receive FIFOs (pointed to by the receive pop
pointers) is latched along with current status information at any falling
edge on the SPI chip select line. This assures that the information is
coherent in case further DSI activity causes any changes.
If the user violates normal procedure and writes the transmit data buffer
when TFNFx = 0 (indicating the FIFO is full), the new transfer is ignored.
Shows a typical burst transmission between the SPI of the
host MCU and the SPI in the MC68HC55. This example assumes the
DSI/D register pointer was pointing at the STATUS register (100) before
the start of the burst. The first SPI transfer is the command from the host
MCU (write address 000 in this case). During this first transfer, the data
returned to the MCU is the data that was latched from the status register
at the falling edge on CS. During the next SPI transfer, the data from
DSI0H (receive FIFO at pop pointer) is sent back to the MCU while new
data is written to DSI0H (transmit FIFO at push pointer). Notice CS
remains low throughout the whole burst sequence. As each SPI transfer
completes, the DSI/D register pointer is incremented to point at the next
register. At the end of this burst, the register pointer is left pointing to the
status register so it is ready for the next SPI burst.
Figure 4-7. SPI Burst Transfer Example
COMMAND - WRT 000
READ STATUS
WRITE DSI0H (000)
READ DSI0H (000)
WRITE DSI0L (001)
READ DSI0L (001)
WRITE DSI1H (010)
READ DSI1H (010)
WRITE DSI1L (011)
READ DSI1L (011)
CLK
DI
DO
CS
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