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參數(shù)資料
| 型號： | MC68HC55CD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 2/40頁 |
| 文件大?。?/td> | 284K |
| 代理商： | MC68HC55CD |
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MC68HC55 Technical Data
Technical Data
MC68HC55
10
Registers and Bit Descriptions
3.2 DSI Channel 1 Data Registers
For the description of DSI1H and DSI1L, refer to 3.1 DSI Channel 0
3.3 DSI Status Register
This 8-bit register provides status information for both channels of the
DSI/D. A copy of this register is latched at the falling edge of the SPI chip
select to avoid asynchronous problems due to bits changing during an
SPI transfer. Any changes that occur while chip select remains low (due
to SPI data reads or writes or reception of new DSI data, etc.) will not be
Address:
$010
Bit 7
654321
Bit 0
Read:
BIt 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
00000000
Figure 3-3. DSI Channel 1 Data Register Upper Byte (DSI1H)
Address:
$011
Bit 7
654321
Bit 0
Read:
BIt 7
654321
Bit 0
Write:
Reset:
00000000
Figure 3-4. DSI Channel 1 Data Register Lower Byte (DSI1L)
Address:
$100
Bit 7
654321
Bit 0
Read:
ER1
TFE1
TFNF1
RFNE1
ER0
TFE0
TFNF0
RFNE0
Write:
Reset:
01100110
= Unimplemented
Figure 3-5. DSI Status Register (DSISTAT)
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