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參數(shù)資料
| 型號： | MC68HC55CD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 38/40頁 |
| 文件大?。?/td> | 284K |
| 代理商： | MC68HC55CD |
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MC68HC55 Technical Data
Pin Function Descriptions
MC68HC55
Technical Data
MC68HC55CD Pin Assignments and Descriptions
7
CS
— SPI chip select input. When this signal is high, the DSI/D is
deselected and ignores the other SPI signals. CLK and DI are high
impedance inputs, and DO is high-impedance when CS is high.The first
SPI transfer after CS goes low is always a command to the DSI/D. If CS
is held low for additional SPI transfers, they are considered to be data
related to the previous command.
RESET
— DSI/D system reset. A low level on this pin forces the DSI/D
logic to abort any operation in progress and initialize to a startup
condition.
INT
— This active-low open-drain output signals that some internal
condition needs attention. Separate mask bits are provided for the
receive FIFO not empty and transmit FIFO empty interrupt conditions for
each DSI/D channel (a total of four mask bits). INT remains low as long
as any enabled interrupt condition is still pending.
GND
— Power supply ground return
DSI1R
— DSI channel 1 return. This is the data input signal from the
DSI/P. The DSI/D samples the CMOS level on this pin at the end of a bit
time. This level will correspond to the current sensed on the signal line
of the DSI physical interface by the DSI/P.
DSI1S
— DSI channel 1 signal. This is the data output signal to the
DSI/P. Data bits are pulse length encoded voltage levels on this signal
line. A logic 0 starts with a falling edge on DSI1S and is low for two-thirds
of the bit time and then high for one-third of the bit time. A logic 1 starts
with a falling edge on DSI1S and is low for one-third of the bit time and
then high for two-thirds of the bit time.
DSI1F
— DSI channel 1 frame.This output idles high and is driven low
during each transfer frame.
DSI0R
— DSI channel 0 return. This is the data input signal from the
DSI/P. The DSI/D samples the CMOS level on this pin at the end of a bit
time. This level will correspond to the current sensed on the signal line
of the DSI physical interface by the DSI/P.
DSI0S
— DSI channel 0 signal. This is the data output signal to the
DSI/P. Data bits are pulse length encoded voltage levels on this signal
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