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參數(shù)資料
| 型號： | MC68HC55CD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 37/40頁 |
| 文件大?。?/td> | 284K |
| 代理商： | MC68HC55CD |
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MC68HC55 Technical Data
Technical Data
MC68HC55
6
MC68HC55CD Pin Assignments and Descriptions
2.2 Pin Function Descriptions
SCLK
— This clock input controls bit and frame timing for messages
between the DSI/D and the DSI/P. The length of a bit time may be
configured to be 3, 6, 12, or 24 periods of SCLK by the setting of the
CDIV0[B:A] and CDIV1[B:A] bit fields (the setting for each DSI/D
channel is independently controlled). SCLK is relatively slow (nom.
15 kHz to 450 kHz) compared to the SPI clock (nom. 4 MHz).
CLK
— This is the SPI clock signal from the MCU. The DSI/D is a slave
SPI device.
DI
— SPI data in to DSI/D (MOSI pin of MCU).
DO
— SPI data out from DSI/D (MISO pin of MCU).
Table 2-1. Pin Information
Pin #
Pin Name
Description
Direction
Relative to DSI/D
Source/
Destination
1
SCLK
System clock
Input
From MCU
2
CLK
SPI clock
Input
SCK out from MCU
3
DI
SPI data in to DSI/D
Input
MOSI from MCU
4
DO
SPI data out from DSI/D
Three-state output
MISO to MCU
5
CS
SPI chip select
Active low input
Port output from MCU
6
RESET
DSI/D reset
Active low input
RESET of MCU system
7
INT
Interrupt output
Active low output
(open-drain)
To IRQ input of MCU
8
GND
Supply common
—
Supply common
9
DSI1R
DSI channel 1 return
CMOS input
From DSI_R of DSI/P
10
DSI1S
DSI channel 1 signal
CMOS output
To DSI_S of DSI/P
11
DSI1F
DSI channel 1 frame
CMOS output
To DSI_F of DSI/P
12
N/C
No connection
—
13
DSI0R
DSI channel 0 return
CMOS input
From DSI_R of DSI/P
14
DSI0S
DSI channel 0 signal
CMOS output
To DSI_S of DSI/P
15
DSI0F
DSI channel 0 frame
CMOS output
To DSI_F of DSI/P
16
VDD
Positive supply
—
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