參數(shù)資料
型號(hào)： MC68HC55CD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), SERIAL COMM CONTROLLER, PDSO16
封裝： SOIC-16
文件頁(yè)數(shù)： 6/40頁(yè)
文件大?。?/td> 284K
代理商： MC68HC55CD
MC68HC55 Technical Data
Technical Data
MC68HC55
14
Registers and Bit Descriptions
frame to the beginning of the next frame. The length of a bit time
depends upon the SCLK input frequency and the current setting in the
CDIV0[B:A] bits.
RIE0 — Receive Interrupt Enable (Channel 0) Bit
0 = Receive interrupt disabled; RFNE0 status does not affect INT
pin.
1 = Receive interrupt enabled; whenever the RFNE0 status flag is
1, the INT pin will be low to request an interrupt.
TIE0 — Transmit Interrupt Enable (Channel 0) Bit
0 = Transmit interrupt disabled; TFE0 status does not affect INT
pin.
1 = Transmit interrupt enabled, whenever the TFE0 status flag is 1,
the INT pin will be low to request an interrupt.
MS0 — Message Size (Channel 0) Bit
0 = 16 data bits plus 4 CRC bits data bits 15 through 0 then 4 CRC
bits
1 = 8 data bits plus 4 CRC bits data bits 7 through 0 then 4 CRC bits
If the DSI0CTRL register is written while a transfer is in progress, the
transfer is aborted without being completed.
Table 3-3. DLY0 Frame Spacing Information
DLY0[B:A]
Minimum Delay Between Frames
(Bit Times)
0:0
4
0:1
8
1:0
16
1:1
32
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