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參數(shù)資料
| 型號： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 90/191頁 |
| 文件大?。?/td> | 1311K |
| 代理商： | MC68306PV16 |
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MOTOROLA
MC68306 USER'S MANUAL
1- 3
these instructions, including predecrement and postincrement, which allow simple stack
and queue maintenance and scaled indexing for efficient table accesses. Data types and
addressing modes are supported orthogonally by all data operations and with all
appropriate addressing modes. Position-independent code is easily written.
Like all M68000 family processors, the MC68EC000 core recognizes interrupts of seven
different priority levels and allows either an automatic vector or a peripheral-supplied
vector to direct the processor to the desired service routine. Internal trap exceptions
ensure proper instruction execution with good addresses and data, allow operating system
intervention in special situations, and permit instruction tracing. Hardware signals can
either terminate or rerun bad memory accesses before instructions process data
incorrectly. The EC000 core provides 2.4 MIPS at 16.67 MHz.
1.2 ON-CHIP PERIPHERALS
To improve total system throughput and reduce part count, board size, and cost of system
implementation, the M68300 family integrates on-chip, intelligent peripheral modules and
typical glue logic. The functions on the MC68306 include two serial channels, a
timer/counter, a DRAM controller, a parallel port, and system glue logic.
1.2.1 Serial Module
Most digital systems use serial I/O to communicate with host computers, operator
terminals, or remote devices. The MC68306 contains a two-channel, full-duplex UART
with an integrated timer. An on-chip baud rate generator provides standard baud rates up
the 38.4K baud to each channel's receiver and transmitter. The serial module is identical
to the MC68681/MC2681 DUART.
Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8
bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive
buffers and two-byte transmit buffers minimize CPU service calls. Each channel provides
a wide variety of error detection and maskable interrupt capability. Full-duplex, autoecho
loopback, local loopback, and remote loopback modes can be selected. Multidrop
applications are also supported.
A 3.6864 MHz crystal drives the baud rate generators. Each transmit and receive channel
can be programmed for a different baud rate. Full modem support is provided with
separate request-to-send (RTS) and clear-to-send (CTS) signals for each channel.
The integrated 16-bit timer/counter can operate in a counter mode or a timer mode. The
timer/counter can function as a system stopwatch, a real-time single interrupt generator,
or a device watchdog when in counter mode. In timer mode, the timer/counter can be
used as a programmable clock source for channels A and B, a periodic interrupt
generator, or a variable duty cycle square-wave generator.
1.2.2 DRAM Controller
DRAM is used in many systems since it is the least expensive form of high-speed storage
available. However, considerable design effort is often spent designing the interface
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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