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參數(shù)資料
| 型號(hào)： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 41/191頁(yè) |
| 文件大?。?/td> | 1311K |
| 代理商： | MC68306PV16 |
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MOTOROLA
MC68306 USER'S MANUAL
6-27
Table 6-7. MISCx Control Bits
MISC2
MISC1
MISC0
Command
0
No Command
0
1
Reset Mode Register Pointer
0
1
0
Reset Receiver
0
1
Reset Transmitter
1
0
Reset Error Status
1
0
1
Reset Break-Change Interrupt
1
0
Start Break
1
Stop Break
Reset Mode Register Pointer—The reset mode register pointer command causes the
mode register pointer to point to DUMR1.
Reset Receiver—The reset receiver command resets the channel receiver. The receiver
is immediately disabled, the FFULL and RxRDY bits in the DUSR are cleared, and the
receiver FIFO pointer is reinitialized. All other registers are unaltered. This command
should be used in lieu of the receiver disable command whenever the receiver
configuration is changed because it places the receiver in a known state.
Reset Transmitter—The reset transmitter command resets the channel transmitter. The
transmitter is immediately disabled, and the TxEMP and TxRDY bits in the DUSR are
cleared. All other registers are unaltered. This command should be used in lieu of the
transmitter disable command whenever the transmitter configuration is changed
because it places the transmitter in a known state.
Reset Error Status—The reset error status command clears the channel's RB, FE, PE,
and OE bits (in the DUSR). This command is also used in the block mode to clear all
error bits after a data block is received.
Reset Break-Change Interrupt—The reset break-change interrupt command clears the
delta break (DBx) bits in the DUISR.
Start Break—The start break command forces the channel's TxDx low. If the transmitter
is empty, the start of the break conditions can be delayed up to one bit time. If the
transmitter is active, the break begins when transmission of the character is complete. If
a character is in the transmitter shift register, the start of the break is delayed until the
character is transmitted. If the transmitter holding register has a character, that
character is transmitted after the break. The transmitter must be enabled for this
command to be accepted. The state of the CTS≈ input is ignored for this command.
Stop Break—The stop break command causes the channel's TxDx to go high (mark)
within two bit times. Characters stored in the transmitter buffer, if any, are transmitted.
TC1–TC0—Transmitter Commands
These bits select a single command as listed in Table 6-8.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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