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參數(shù)資料
| 型號： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 101/191頁 |
| 文件大?。?/td> | 1311K |
| 代理商： | MC68306PV16 |
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1- 4
MC68306 USER'S MANUAL
MOTOROLA
between the processor and DRAM. The MC68306 contains a full DRAM controller, greatly
reducing design time and complexity.
The DRAM controller provides row address strobe ( RAS) and column address strobe
(CAS) signals for two separate banks of DRAMs. Each bank can include up to 16 devices;
up to 15 multiplexed address lines are also available. Thus, using 4M x 1 DRAMs, up to
16 Mbytes of DRAM are supported; with 16M x 1 DRAMs, up to 64 Mbytes of DRAM are
supported. A programmable refresh timer provides CAS-before- RAS refreshes at
designated intervals.
The DRAM controller has its own address registers that control the address range
selected by each RAS and CAS signal, leaving the eight integrated chip selects free for
other system peripherals. DRAM accesses are zero wait states using 80-ns DRAMs.
1.2.3 Chip Selects
The MC68306 provides up to eight programmable chip select outputs, in most cases
eliminating the need for external address decoding. All handshaking and timing signals
are provided, with up to 950-ns access times. Each chip select can access a 16 Mbyte
address space located anywhere in the 4-Gbyte address range. Internal registers allow
the base address, range, and cycle duration of each chip select to be independently
programmed. After reset, chip select (CS0) responds to all accesses until the chip selects
have been properly programmed. Four of the chip selects are multiplexed with the most
significant address bits (A23–A20). The address mode (AMODE) input determines the
functions of these outputs.
1.2.4 Parallel Ports
Two 8-bit parallel ports are provided. The port pins can be individually programmed to be
inputs or outputs. If the pins are programmed to be inputs, the value on those pins can be
read by accessing an on-board register. If the pins are programmed to be outputs, the
pins will reflect the value programmed into another on-board register. The port B pins are
multiplexed with four interrupt request and four interrupt acknowledge lines. The function
of these pins is controlled by the internal registers.
1.2.5 Interrupt Controller
Seven input signals are provided to trigger an external interrupt, one for each of the seven
priority levels supported. Each input can be programmed to be active high or active low.
Seven separate outputs indicate the priority level of the interrupt being serviced. Interrupts
at each priority level can be pre-programmed to go to the default service routine. For
maximum flexibility, interrupts can be vectored to the correct service routine by the
interrupting device.
1.2.6 Clock
To save on system costs, the MC68306 has an on-board oscillator that can be driven with
a 16.67-MHz crystal. A bus clock output is provided by a CLKOUT pin. Alternatively, an
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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