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參數(shù)資料
| 型號： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 177/191頁 |
| 文件大?。?/td> | 1311K |
| 代理商： | MC68306PV16 |
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4- 18
MC68306 USER'S MANUAL
MOTOROLA
the interrupt is considered spurious, and the generated vector number references the
spurious interrupt vector. The processor then proceeds with the usual exception
processing. The saved value of the program counter is the address of the instruction that
would have been executed had the interrupt not been taken. The appropriate interrupt
vector is fetched and loaded into the program counter, and normal instruction execution
commences in the interrupt handling routine.
4.6.3 Uninitialized Interrupt Exception
An interrupting device provides a EC000 core interrupt vector number and asserts data
transfer acknowledge (DTACK) or bus error ( BERR ) during an interrupt acknowledge
cycle by the EC000 core. If the vector register has not been initialized, the responding
M68000 family peripheral provides vector number 15, the uninitialized interrupt vector.
This response conforms to a uniform way to recover from a programming error.
4.6.4 Spurious Interrupt Exception
During the interrupt acknowledge cycle, if no device responds by asserting DTACK, BERR
should be asserted to terminate the vector acquisition. The processor separates the
processing of this error from bus error by forming a short format exception stack and
fetching the spurious interrupt vector instead of the bus error vector. The processor then
proceeds with the usual exception processing.
4.6.5 Instruction Traps
Traps are exceptions caused by instructions; they occur when a processor recognizes an
abnormal condition during instruction execution or when an instruction is executed that
normally traps during execution.
Exception processing for traps is straightforward. The status register is copied; the
supervisor mode is entered; and tracing is turned off. The vector number is internally
generated; for the TRAP instruction, part of the vector number comes from the instruction
itself. The program counter, and the copy of the status register are saved on the
supervisor stack. The saved value of the program counter is the address of the instruction
following the instruction that generated the trap. Finally, instruction execution commences
at the address in the exception vector.
Some instructions are used specifically to generate traps. The TRAP instruction always
forces an exception and is useful for implementing system calls for user programs. The
TRAPV and CHK instructions force an exception if the user program detects a run-time
error, which may be an arithmetic overflow or a subscript out of bounds. A signed divide
(DIVS) or unsigned divide (DIVU) instruction forces an exception if a division operation is
attempted with a divisor of zero.
4.6.6 Illegal and Unimplemented Instructions
Illegal instruction is the term used to refer to any of the word bit patterns that do not match
the bit pattern of the first word of a legal processor instruction. If such an instruction is
fetched, an illegal instruction exception occurs. Motorola reserves the right to define
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