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參數(shù)資料
| 型號： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 179/191頁 |
| 文件大小： | 1311K |
| 代理商： | MC68306PV16 |
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4- 20
MC68306 USER'S MANUAL
MOTOROLA
instruction is not executed because an interrupt is taken or because the instruction is
illegal or privileged, the trace exception does not occur. The trace exception also does not
occur if the instruction is aborted by a reset, bus error, or address error exception. If the
instruction is executed and an interrupt is pending on completion, the trace exception is
processed before the interrupt exception. During the execution of the instruction, if an
exception is forced by that instruction, the exception processing for the instruction
exception occurs before that of the trace exception.
As an extreme illustration of these rules, consider the arrival of an interrupt during the
execution of a TRAP instruction while tracing is enabled. First, the trap exception is
processed, then the trace exception, and finally the interrupt exception. Instruction
execution resumes in the interrupt handler routine.
After the execution of the instruction is complete and before the start of the next
instruction, exception processing for a trace begins. A copy is made of the status register.
The transition to supervisor mode is made, and the T-bit of the status register is turned off,
disabling further tracing. The vector number is generated to reference the trace exception
vector, and the current program counter and the copy of the status register are saved on
the supervisor stack. The saved value of the program counter is the address of the next
instruction. Instruction execution commences at the address contained in the trace
exception vector.
4.6.9 Bus Error
When a bus error exception occurs, the current bus cycle is aborted. The current
processor activity, whether instruction or exception processing, is terminated, and the
processor immediately begins exception processing.
Exception processing for a bus error follows the usual sequence of steps. The status
register is copied, the supervisor mode is entered, and tracing is turned off. The vector
number is generated to refer to the bus error vector. Since the processor is fetching the
instruction or an operand when the error occurs, the context of the processor is more
detailed. To save more of this context, additional information is saved on the supervisor
stack. The program counter and the copy of the status register are saved. The value
saved for the program counter is advanced 2–10 bytes beyond the address of the first
word of the instruction that made the reference causing the bus error. If the bus error
occurred during the fetch of the next instruction, the saved program counter has a value in
the vicinity of the current instruction, even if the current instruction is a branch, a jump, or
a return instruction. In addition to the usual information, the processor saves its internal
copy of the first word of the instruction being processed and the address being accessed
by the aborted bus cycle. Specific information about the access is also saved: type of
access (read or write), processor activity (processing an instruction), and function code
outputs when the bus error occurred. The processor is processing an instruction if it is in
the normal state or processing a group 2 exception; the processor is not processing an
instruction if it is processing a group 0 or a group 1 exception. Figure 4-7 illustrates how
this information is organized on the supervisor stack. If a bus error occurs during the last
step of exception processing, while either reading the exception vector or fetching the
instruction, the value of the program counter is the address of the exception vector.
Although this information is not generally sufficient to effect full recovery from the bus
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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