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參數資料
| 型號： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數： | 171/191頁 |
| 文件大?。?/td> | 1311K |
| 代理商： | MC68306PV16 |
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4- 12
MC68306 USER'S MANUAL
MOTOROLA
4.5 EXCEPTION PROCESSING
This section describes the processing for each type of exception, exception priorities, the
return from an exception, and bus fault recovery. This section also describes the formats
of the exception stack frames.
Exception processing is the activity performed by the processor in preparing to execute a
special routine for any condition that causes an exception. In particular, exception
processing does not include the execution of the routine itself. Exception processing is the
transition from the normal processing of a program to the processing required for any
special internal or external condition that preempts normal processing. External conditions
that cause exceptions are interrupts from external devices, bus errors, and resets. Internal
conditions that cause exceptions are instructions, address errors, and tracing. For
example, the TRAP, TRAPV, CHK, RTE, and DIV instructions can generate exceptions as
part of their normal execution. In addition, illegal instructions and privilege violations cause
exceptions. Exception processing uses an exception vector table and an exception stack
frame.
Exception processing occurs in four functional steps. However, all individual bus cycles
associated with exception processing (vector acquisition, stacking, etc.) are not
guaranteed to occur in the order in which they are described in this section. Figure 4-3
illustrates a general flowchart for the steps taken by the processor during exception
processing.
During the first step, the processor makes an internal copy of the status register (SR).
Then the processor changes to the supervisor mode by setting the S-bit and inhibits
tracing of the exception handler by clearing the trace enable (T) bit in the SR. For the
reset and interrupt exceptions, the processor also updates the interrupt priority mask in
the SR.
During the second step, the processor determines the vector number for the exception.
For interrupts, the processor performs an interrupt acknowledge bus cycle to obtain the
vector number. For all other exceptions, internal logic provides the vector number. This
vector number is used in the last step to calculate the address of the exception vector.
Throughout this section, vector numbers are given in decimal notation.
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