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參數(shù)資料
| 型號(hào)： | MC68306PV16 |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 29/191頁(yè) |
| 文件大小： | 1311K |
| 代理商： | MC68306PV16 |
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6- 16
MC68306 USER'S MANUAL
MOTOROLA
In either case, the data bits are loaded into the data portion of the stack while the A/D bit
is loaded into the status portion of the stack normally used for a parity error (DUSR bit 5).
Framing error, overrun error, and break detection operate normally. The A/D bit takes the
place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this
mode may still contain error detection and correction information. One way to provide
error detection, if 8-bit characters are not required, is to use software to calculate parity
and append it to the 5-, 6-, or 7-bit character.
6.3.5 Counter/Timer
The 16-bit counter/timer can operate in a counter mode or a timer mode. In either mode,
the counter/timer clock source can be programmed to come from several sources and the
counter/timer output can be programmed to appear on output port pin OP3 (inverted). The
preload value stored in the concatenation of the counter/timer upper register (DUCTUR)
and the counter/timer lower register (DUCTLR) can be from $0002 through $FFFF and
this value can be changed at any time. In the counter mode, the counter/timer can be
started and stopped by the CPU. Thus, this mode allows the counter/timer to be used as a
system stopwatch, a real-time single interrupt generator, or a device watchdog. In the
timer mode, the counter/timer runs continuously and cannot be started or stopped by the
CPU. Instead, the CPU only resets the counter/timer. Thus, this mode allows the
counter/timer to be used as a programmable clock source for channels A and B, periodic
interrupt generator, or a variable duty cycle square-wave generator. Upon power-up and
after reset, the counter/timer operates in counter mode.
6.3.5.1 COUNTER MODE. In the counter mode, the counter/timer counts down from the
preload value using the programmed counter clock source. The counter clock source can
be the X1/CLK pin, the channel A transmitter clock, the channel B transmitter clock, or an
external clock on the input port pin IP2. The CPU can start and stop the counter and can
read the count value (DUCUR:DUCLR). When a read at the start counter command
address is performed, the counter initializes itself with the preload value and begins a
countdown sequence. Upon reaching $0000 (terminal count), the counter sets the
counter/timer-output and the counter/timer ready bit in the interrupt status register
(DUISR[3]), rolls over from $0000 to $FFFF, and continues counting. The counter can be
programmed to generate an interrupt request for this condition on the IRQ or TIRQ output.
If the preload value is changed by the CPU, the counter will not recognize the new value
until it receives the next start counter command (and must reinitialize itself). When a read
at the stop counter command address is performed, the counter stops the countdown
sequence and clears the C/T output and DUISR[3]. The count value should only be read
while the counter is stopped. This is because only one of the count registers (either
DUCUR or DUCLR) can be read at a time and if the counter is running, a decrement of
DUCLR that requires a borrow from the DUCUR could take place between the two reads.
6.3.5.2 TIMER MODE. In the timer mode, the counter/timer generates a square-wave
output derived from the programmed timer input (clock source). The timer clock source is
X1/CLK or an external input on input port pin IP2, divided by one or sixteen. The square
wave generated by the timer has a period of twice the preload value times the period of
the clock source, is available as a clock source for both communications channels, and
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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