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| 型號(hào)： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁數(shù)： | 37/191頁 |
| 文件大小： | 1311K |
| 代理商： | MC68306PV16 |
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MOTOROLA
MC68306 USER'S MANUAL
6-23
FE—Framing Error
1 = A stop bit was not detected when the corresponding data character in the FIFO
was received. The stop-bit check is made in the middle of the first stop-bit
position. The bit is valid only when the RxRDY bit is set.
0 = No framing error has occurred.
PE—Parity Error
1 = When the with parity or force parity mode is programmed in the DUMR1, the
corresponding character in the FIFO was received with incorrect parity. When the
multidrop mode is programmed, this bit stores the received A/D bit. This bit is
valid only when the RxRDY bit is set.
0 = No parity error has occurred.
OE—Overrun Error
1 = One or more characters in the received data stream have been lost. This bit is
set upon receipt of a new character when the FIFO is full and a character is
already in the shift register waiting for an empty FIFO position. When this occurs,
the character in the receiver shift register and its break detect, framing error
status, and parity error, if any, are lost. This bit is cleared by the reset error status
command in the DUCR.
0 = No overrun has occurred.
TxEMP—Transmitter Empty
1 = The channel transmitter has underrun (both the transmitter holding register and
transmitter shift registers are empty). This bit is set after transmission of the last
stop bit of a character if there are no characters in the transmitter holding register
awaiting transmission.
0 = The transmitter buffer is not empty. Either a character is currently being shifted
out, or the transmitter is disabled. The transmitter is enabled/disabled by
programming the TCx bits in the DUCR.
TxRDY—Transmitter Ready
This bit is duplicated in the DUISR; bit 0 for channel A and bit 4 for channel B.
1 = The transmitter holding register is empty and ready to be loaded with a character.
This bit is set when the character is transferred to the transmitter shift register.
This bit is also set when the transmitter is first enabled. Characters loaded into
the transmitter holding register while the transmitter is disabled are not
transmitted.
0 = The transmitter holding register was loaded by the CPU, or the transmitter is
disabled.
FFULL—FIFO Full
1 = A character has been received in channel B and is waiting in the receiver buffer
FIFO.
0 = The FIFO is not full, but may contain up to two unread characters.
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