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參數(shù)資料
| 型號(hào)： | MC68306PV16 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, MICROPROCESSOR, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 176/191頁(yè) |
| 文件大小： | 1311K |
| 代理商： | MC68306PV16 |
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MOTOROLA
MC68306 USER'S MANUAL
4- 17
4.6.1 Reset Exception
The reset exception corresponds to the highest exception level. The processing of the
reset exception is performed for system initiation and recovery from catastrophic failure.
Any processing in progress at the time of the reset is aborted and cannot be recovered.
The processor is forced into the supervisor state, and the trace state is forced off. The
interrupt priority mask is set at level 7. The vector number is internally generated to
reference the reset exception vector at location 0 in the supervisor program space.
Because no assumptions can be made about the validity of register contents, in particular
the SSP, neither the program counter nor the status register are saved. The address in
the first two words of the reset exception vector is fetched as the initial SSP, and the
address in the last two words of the reset exception vector is fetched as the initial program
counter. Finally, instruction execution is started at the address in the program counter.
The initial program counter should point to the power-up/restart code.
The RESET instruction does not cause a reset exception; it asserts the RESET signal to
reset external devices, which allows the software to reset the system to a known state and
continue processing with the next instruction.
4.6.2 Interrupt Exceptions
Seven levels of interrupt priorities are provided, numbered from 1–7. Level 7 has the
highest priority. Devices can be chained externally within interrupt priority levels, allowing
an unlimited number of peripheral devices to interrupt the processor. The status register
contains a 3-bit mask indicating the current interrupt priority, and interrupts are inhibited
for all priority levels less than or equal to the current priority. Priority level 7 is a special
case. Level 7 interrupts cannot be inhibited by the interrupt priority mask, thus providing a
non-maskable interrupt capability. An interrupt is generated each time the interrupt
request level changes from some lower level to level 7. A level 7 interrupt may still be
caused by the level comparison if the request level is a 7 and the processor priority is set
to a lower level by an instruction.
An interrupt request is made to the processor by encoding the interrupt request level on
the IPL2 –IPL0; a zero indicates no interrupt request. Interrupt requests arriving at the
processor do not force immediate exception processing, but the requests are made
pending. Pending interrupts are detected between instruction executions. If the priority of
the pending interrupt is lower than or equal to the current processor priority, execution
continues with the next instruction, and the interrupt exception processing is postponed
until the priority of the pending interrupt becomes greater than the current processor
priority.
If the priority of the pending interrupt is greater than the current processor priority, the
exception processing sequence is started. A copy of the status register is saved; the
privilege mode is set to supervisor mode; tracing is suppressed; and the processor priority
level is set to the level of the interrupt being acknowledged. The processor fetches the
vector number from the interrupting device by executing an interrupt acknowledge cycle,
which displays the level number of the interrupt being acknowledged on the address bus.
If external logic requests an automatic vector, the processor internally generates a vector
number corresponding to the interrupt level number. If external logic indicates a bus error,
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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