參數(shù)資料
型號(hào): M306H3FCFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116
封裝: 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù): 99/135頁
文件大小: 2583K
代理商: M306H3FCFP
Rev.1.00
2004.03.23
page 66 of 320
M306H3MC-XXXFP/FCFP
Interrupt sources
7
Level that is set to IPL
_______
Watchdog timer, NMI
_________
Software, address match, DBC, single-step
Not changed
Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 2.7.5 is set in the IPL. Shown in Table 2.7.5 are the IPL values of software and special interrupts
when they are accepted.
Table 2.7.5. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted
Instruction
Interrupt sequence
Instruction in
interrupt routine
Time
Interrupt response time
(a)
(b)
Interrupt request acknowledged
Interrupt request generated
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt vector address
Even
Odd
SP value
Even
Odd
Even
Odd
16-Bit bus, without wait
18 cycles
19 cycles
20 cycles
8-Bit bus, without wait
20 cycles
Figure 2.7.5. Interrupt response time
Interrupt Response Time
Figure 2.7.5 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) in Figure 2.7.5) and a time during which the interrupt
sequence is executed ((b) in Figure 2.7.5).
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