參數(shù)資料
型號(hào)： M306H3FCFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116
封裝： 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁(yè)數(shù)： 41/135頁(yè)
文件大?。?/td> 2583K
代理商： M306H3FCFP
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Rev.1.00
2004.03.23
page 135 of 320
M306H3MC-XXXFP/FCFP
Function
I2C mode (SMD2 to SMD0 = 0102, IICM = 1)
Clock synchronous serial I/O
mode (SMD2 to SMD0 = 0012,
IICM = 0)
Factor of interrupt number
15, 17 and 19 (Note 1, 6)
No acknowledgment
detection (NACK)
Rising edge of SCLi 9th bit
Factor of interrupt number
16, 18 and 20 (Note 1, 6)
Start condition detection or stop condition detection
(Refer to “Table 2.11.13. STSPSEL Bit Functions”)
UARTi transmission output
delay
Functions of P63, P67 and
P70 pins
Noise filter width
Read RxDi and SCLi pin
levels
Factor of interrupt number
6, 7 and 10 (Note 1, 5, 7)
Acknowledgment detection
(ACK)
Rising edge of SCLi 9th bit
Initial value of TxDi and
SDAi outputs
UARTi transmission
Transmission started or
completed (selected by UiIRS)
UARTi reception
When 8th bit received
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Not delayed
TxDi output
RxDi input
CLKi input or output selected
15ns
Possible when the
corresponding port direction bit
= 0
CKPOL = 0 (H)
CKPOL = 1 (L)
Delayed
SDAi input/output
SCLi input/output
(Cannot be used in I2C mode)
Initial and end values of
SCLi
H
200ns
Always possible no matter how the corresponding port direction bit is set
The value set in the port register before setting I2C mode (Note 2)
Timing for transferring data
from the UART reception
shift register to the UiRB
register
IICM2 = 0
(NACK/ACK interrupt)
IICM2 = 1
(UART transmit/ receive interrupt)
CKPH = 1
(Clock delay)
CKPH = 1
(Clock delay)
UARTi transmission
Rising edge of
SCLi 9th bit
UARTi transmission
Falling edge of SCLi
next to the 9th bit
UARTi reception
Falling edge of SCLi 9th bit
CKPOL = 0 (rising edge)
CKPOL = 1 (falling edge)
Rising edge of SCLi 9th bit
Falling edge of
SCLi 9th bit
Falling and rising
edges of SCLi 9th
bit
Functions of P62, P66 and
P71 pins
Functions of P61, P65 and
P72 pins
i = 0 to 2
Note 1: If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to “precautions for interrupts” of the Usage Notes Reference Book.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to
clear the IR bit to “0” (interrupt not requested) after changing those bits.
SMD2 to SMD0 bits in the UiMR register, IICM bit in the UiSMR register, IICM2 bit in the UiSMR2 register, CKPH bit in the
UiSMR3 register
Note 2: Set the initial value of SDAi output while the UiMR register’s SMD2 to SMD0 bits = ‘0002’ (serial I/O disabled).
Note 3: Second data transfer to UiRB register (Rising edge of SCLi 9th bit)
Note 4: First data transfer to UiRB register (Falling edge of SCLi 9th bit)
Note 5: Refer to “Figure 2.11.24. STSPSEL Bit Functions”.
Note 6: Refer to “Figure 2.11.22. Transfer to UiRB Register and Interrupt Timing”
.
Note 7: When using UART0, be sure to set the IFSR26 bit in the IFSR2A register to “1” (cause of interrupt: UART0 bus collision).
When using UART1, be sure to set the IFSR26 bit in the IFSR2A register to “1” (cause of interrupt: UART1 bus collision).
DMA1 factor (Refer to Fig
2.11.22)
UARTi reception
Acknowledgment detection
(ACK)
UARTi reception
Falling edge of SCLi 9th bit
Store received data
1st to 8th bits are stored in
UiRB register bit 0 to bit 7
1st to 8th bits are stored in
UiRB register bit 7 to bit 0
1st to 7th bits are stored in UiRB register
bit 6 to bit 0, with 8th bit stored in UiRB
register bit 8
L
Read UiRB register
Bit 6 to bit 0 as bit 7
to bit 1, and bit 8 as
bit 0 (Note 4)
Read received data
UiRB register status is read
directly as is
CKPH = 0
(No clock delay)
CKPH = 0
(No clock delay)
H
L
1st to 8th bits are
stored in UiRB
register bit 7 to bit 0
(Note 3)
Table 2.11.12. I2C Mode Functions
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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