參數(shù)資料
型號： M306H3FCFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116
封裝： 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù)： 33/135頁
文件大?。?/td> 2583K
代理商： M306H3FCFP
Rev.1.00
2004.03.23
page 128 of 320
M306H3MC-XXXFP/FCFP
Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
Figure 2.11.16. Receive Operation
D0
Start bit
Sampled “L”
UiBRG count
source
RxDi
Transfer clock
RTSi
Stop bit
“1”
“0”
“1”
“H”
“L”
“0”
“1”
Reception triggered when transfer clock
is generated by falling edge of start bit
UiC1 register
RE bit
UiC1 register
RI bit
SiRIC register
IR bit
Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program
Receive data taken in
D7
D1
Transferred from UARTi receive
register to UiRB register
The above timing diagram applies to the case where the register bits are set as follows:
UiMR register PRYE bit = 0 (parity disabled)
UiMR register STPS bit = 0 (1 stop bit)
UiC0 register CRD bit = 0 (CTSi/RTSi enabled), CRS bit = 1 (RTSi selected)
i = 0 to 2
(a) LSB First/MSB First Select Function
As shown in Figure 2.11.17, use the UiC0 register’s UFORM bit to select the transfer format. This
function is valid when transfer data is 8 bits long.
Figure 2.11.17. Transfer Format
(1) When UiC0 register's UFORM bit = 0 (LSB first)
(2) When UiC0 register's UFORM bit = 1 (MSB first)
Note: This applies to the case where the UiC0 register’s CKPOL bit = 0 (
transmit data output at the falling edge and the receive data taken
in at the rising edge of the transfer clock), the UiC1 register’s UiLCH
bit = 0 (no reverse), UiMR register's STPS bit = 0 (1 stop bit) and
UiMR register's PRYE bit = 1 (parity enabled).
D1
D2
D3
D4
D5
D6
SP
D0
D1
D2
D3
D4
D5
D6
SP
D0
TXDi
RXDi
CLKi
D6
D5
D4
D3
D2
D1
D0
D7
TXDi
RXDi
CLKi
ST
D7
P
D7
P
SP
ST
P
D6
D5
D4
D3
D2
D1
D0
D7
ST : Start bit
P : Parity bit
SP : Stop bit
i = 0 to 2
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