參數(shù)資料
型號(hào): M306H3FCFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116
封裝: 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù): 121/135頁
文件大小: 2583K
代理商: M306H3FCFP
Rev.1.00
2004.03.23
page 86 of 320
M306H3MC-XXXFP/FCFP
2.9.5 Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the
DMA requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes
DMAC operation when DMA0 and DMA1 requests are detected active in the same sampling period.
Figure 2.9.6 shows an example of DMA transfer effected by external factors.
DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request
are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is returned to the
CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is
completed, the bus arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 2.9.6, occurs more than one time, the DMAS bit is set to “0” as soon as
getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
Refer to “(7) Hold Signal in 2.4.2 Bus Control” for details about bus arbitration between the CPU and
DMA.
BCLK
DMA0
DMA1
DMA0
request bit
DMA1
request bit
CPU
INT0
INT1
Bus
arbitration
An example where DMA requests for external causes are detected active at the same
Figure 2.9.6. DMA Transfer by External Factors
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