參數(shù)資料
型號: M306H3FCFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116
封裝: 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù): 37/135頁
文件大?。?/td> 2583K
代理商: M306H3FCFP
Rev.1.00
2004.03.23
page 131 of 320
M306H3MC-XXXFP/FCFP
2.11.4 Special Mode 1 (I2C mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 2.11.9 lists the speci-
fications of the I2C mode. Table 2.11.10 lists the registers used in the I2C mode and the register values
set. Figure 2.11.21 shows the block diagram for I2C mode. Figure 2.11.22 shows SCLi timing.
As shown in Table 2.11.12, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits
to ‘0102’ and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.
Table 2.11.9. I2C Mode Specifications
Item
Specification
Transfer data format
Transfer data length: 8 bits
Transfer clock
During master
UiMR(i=0 to 2) register’s CKDIR bit = “0” (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register
0016 to FF16
During slave
CKDIR bit = “1” (external clock) : Input from SCLi pin
Transmission start condition
Before transmission can start, the following requirements must be met (Note 1)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register = 0 (data present in UiTB register)
Reception start condition
Before reception can start, the following requirements must be met (Note 1)
_ The RE bit of UiC1 register= 1 (reception enabled)
_ The TE bit of UiC1 register= 1 (transmission enabled)
_ The TI bit of UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Error detection
Overrun error (Note 2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
Select function
Arbitration lost
Timing at which the UiRB register’s ABT bit is updated can be selected
SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
Clock phase setting
With or without clock delay selectable
Note 1: When an external clock is selected, the conditions must be met while the external clock is in the
high state.
Note 2: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC
register does not change.
Interrupt request
generation timing
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