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參數資料
| 型號： | M306H3FCFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116 |
| 封裝： | 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116 |
| 文件頁數： | 117/135頁 |
| 文件大?。?/td> | 2583K |
| 代理商： | M306H3FCFP |
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Rev.1.00
2004.03.23
page 82 of 320
M306H3MC-XXXFP/FCFP
2.9.1 Transfer Cycles
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination
write) bus cycle. The number of read and write bus cycles is affected by the source and destination
addresses of transfer. During memory extension and microprocessor modes, it is also affected by the
________
BYTE pin level. Furthermore, the bus cycle itself is extended by a software wait or RDY signal.
(a) Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of
transfer begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer
begins with an odd address, the destination write cycle consists of one more bus cycle than when the
destination address of transfer begins with an even address.
(b) Effect of BYTE Pin Level
During memory extension and microprocessor modes, if 16 bits of data are to be transferred on an 8-
bit data bus (input on the BYTE pin = high), the operation is accomplished by transferring 8 bits of data
twice. Therefore, this operation requires two bus cycles to read data and two bus cycles to write data.
Furthermore, if the DMAC is to access the internal area (internal ROM, internal RAM, or SFR), unlike
in the case of the CPU, the DMAC does it through the data bus width selected by the BYTE pin.
(c) Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of
bus cycles required for that access increases by an amount equal to software wait states.
_______
(d) Effect of RDY Signal
During memory extension and microprocessor modes, DMA transfers to and from an external area
________
are affected by the RDY signal. Refer to “RDY signal”.
Figure 2.9.5 shows the example of the cycles for a source read. For convenience, the destination write
cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality,
the destination write cycle is subject to the same conditions as the source read cycle, with the transfer
cycle changing accordingly. When calculating transfer cycles, take into consideration each condition for
the source read and the destination write cycle, respectively. For example, when data is transferred in 16
bit units using an 8-bit bus ((2) in Figure 2.9.5), two source read bus cycles and two destination write bus
cycles are required.
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| M306H5FGFP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP116 |
| M306N4FGVFP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP100 |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M306H3FCFP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 128KB FLASH 5V 116LQFP - Trays |
| M306H3MC-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER |
| M306H5FGFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER |
| M306H5FGFP#U0 | 功能描述:IC M16C/6H MCU FLASH 116LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:M16C™ M16C/60 標準包裝:160 系列:S08 核心處理器:S08 芯體尺寸:8-位 速度:40MHz 連通性:I²C，LIN，SCI，SPI 外圍設備:LCD，LVD，POR，PWM，WDT 輸入/輸出數:53 程序存儲器容量:32KB（32K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1.9K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數據轉換器:A/D 12x12b 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:64-LQFP 包裝:托盤 |
| M306H5MC-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SNGLE-CHIP 16-BIT CMOS MICROCOMPUTER with DATA ACQUISITION CONTROLLER |
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