參數(shù)資料
型號: M306H3FCFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116
封裝: 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù): 109/135頁
文件大?。?/td> 2583K
代理商: M306H3FCFP
Rev.1.00
2004.03.23
page 75 of 320
M306H3MC-XXXFP/FCFP
2.8 Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit
counter which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to
generate a watchdog timer interrupt request or apply a watchdog timer reset as an operation to be per-
formed when the watchdog timer underflows after reaching the terminal count can be selected using the
PM12 bit of PM1 register. The PM12 bit can only be set to “1” (reset). Once this bit is set to “1”, it cannot
be set to “0” (watchdog timer interrupt) in a program.
Refer to “Watchdog Timer Reset” for the details of watchdog timer reset.
When the main clock is selected for CPU clock, the divide-by-N value for the prescaler can be chosen to
be 16 or 128 using the WDC7 bit of WDC register. If a sub-clock is selected for CPU clock, the divide-by-
N value for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can
be calculated as given below. The period of watchdog timer is, however, subject to an error due to the
prescaler.
For example, when CPU clock = 10 MHz and the divide-by-N value for the prescaler= 16, the watchdog
timer period is approx. 52.4 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset.
Note that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released.
Figure 2.8.1 shows the block diagram of the watchdog timer. Figure 2.8.2 shows the watchdog timer-
related registers.
With main clock chosen for CPU clock
Watchdog timer period =
Prescaler dividing (16 or 128) X Watchdog timer count (32768)
CPU clock
With sub-clock chosen for CPU clock
Watchdog timer period =
Prescaler dividing (2) X Watchdog timer count (32768)
CPU clock
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