參數(shù)資料
型號： M306H3FCFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116
封裝： 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù)： 18/135頁
文件大?。?/td> 2583K
代理商： M306H3FCFP
Rev.1.00
2004.03.23
page 114 of 320
M306H3MC-XXXFP/FCFP
Figure 2.11.6. UCON Register and U0SMR to U2SMR Registers
Note: When using multiple transfer clock output pins, make sure the following conditions are met:
U1MR register’s CKDIR bit = “0” (internal clock)
UART transmit/receive control register 2
Symbol
Address
After reset
UCON
03B016
X00000002
b7
b6
b5
b4
b3
b2
b1
b0
Bit
name
Bit
symbol
RW
Function
CLKMD0
CLKMD1
UART0 transmit
interrupt cause select bit
UART0 continuous
receive mode enable bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enable
UART1 continuous
receive mode enable bit
UART1 CLK/CLKS
select bit 0
UART1 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed (TXEPT = 1)
0 : CLK output is only CLK1
1 : Transfer clock output from multiple pins function
selected
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
U0IRS
U1IRS
U0RRM
U1RRM
UART1 CLK/CLKS
select bit 1 (Note)
Effective when CLKMD1 = “1”
0 : Clock output from CLK1
1 : Clock output from CLKS1
UART2 special mode register (i=0 to 2)
Symbol
Address
After reset
U0SMR to U2SMR
036F16, 037316, 037716
X00000002
b7 b6
b5
b4
b3
b2
b1 b0
Bit
name
Bit
symbol
Function
ABSCS
ACSE
SSS
I2C mode select bit
Bus busy flag
0 : STOP condition detected
1 : START condition detected (busy)
Bus collision detect
sampling clock select bit
Arbitration lost detecting
flag control bit
0 : Other than I2C mode
1 : I2C mode
0 : Update per bit
1 : Update per byte
IICM
ABC
BBS
0 : Not synchronized to RxDi
i
1 : Synchronized to RxDi (Note 3)
Set to “0”
Transmit start condition
select bit
0 : Rising edge of transfer clock
1 : Underflow signal of timer Aj (Note 2)
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of bus collision
Note 1: The BBS bit is set to “0” by writing “0” in a program. (Writing “1” has no effect.).
Note 2: Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer A0 in UART2.
Note 3: When a transfer begins, the SSS bit is set to “0” (Not synchronized to RxDi)
.
(Note1)
RCSP
Separate UART0
CTS/RTS bit
0 : CTS/RTS shared pin
1 : CTS/RTS separated (CTS0 supplied from the P64 pin)
Nothing is assigned. When write, set “0”. When read, its content is indeterminate.
RW
(b7)
RW
(b7)
0
(b3)
Reserved bit
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