參數(shù)資料
型號： M306H3FCFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 10 MHz, MICROCONTROLLER, PQFP116
封裝： 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù)： 5/135頁
文件大?。?/td> 2583K
代理商： M306H3FCFP
Rev.1.00
2004.03.23
page 102 of 320
M306H3MC-XXXFP/FCFP
2.10.2 Timer B
Figure 2.10.14 shows a block diagram of the timer B. Figures 2.10.15 and 2.10.16 show registers related
to the timer B.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits of TBiMR register (i = 0 to
5) to select the desired mode.
Timer mode: The timer counts an internal count source.
Event counter mode: The timer counts pulses from an external device or overflows or underflows of
other timers.
Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Figure 2.10.14. Timer B Block Diagram
Timer Bi mode register (i=0 to 5)
Symbol
Address
After reset
TB0MR to TB2MR
039B16 to 039D16
00XX00002
TB3MR to TB5MR
035B16 to 035D16
00XX00002
Bit name
Function
Bit symbol
RW
b7
b6
b5
b4
b3
b2
b1
b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Must not be set
b1 b0
TCK1
MR3
MR2
MR1
TMOD1
MR0
TMOD0
TCK0
Function varies with each operation
mode
Count source select bit
Operation mode select bit
(Note 1)
(Note 2)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
RW
RO
Function varies with each operation
mode
Clock source selection
Event counter
Timer
Pulse period measuremnet,
pulse width measurement
Reload register
Low-order 8 bits
High-order 8 bits
Data bus low-order bits
Data bus high-order bits
f1 or f2
f8
f32
TBj overflow (Note)
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Can be selected in only
event counter mode
TABSR register
TBSR register
fC32
Polarity switching,
edge pulse
TBiIN
(i = 0 to 5)
Counter reset circuit
Counter
TBi
Address
TBj
Timer B0
039116 039016
Timer B2
Timer B1
039316 039216
Timer B0
Timer B2
039516 039416
Timer B1
Timer B3
035116 035016
Timer B5
Timer B4
035316 035216
Timer B3
Timer B5
035516 035416
Timer B4
Clock selection
Note: Overflow or underflow.
Figure 2.10.15. TB0MR to TB5MR Registers
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