
LXT6251A
—
21 E1 SDH Mapper
68
Datasheet
4. The results are shifted out and next test stimuli shifted into the BSR.
9.1.1.2
SAMPLE/PRELOAD (
‘
b01)
This instruction allows a snapshot of the normal operation of the LXT6251A. The boundary scan
register is connected between the TDI and TDO for any data shifts while this instruction is active.
All BSR cells capture data present at their inputs on the rising edge of JTCK during the
CAPTURE-DR state. No action is taken during the UPDATE-DR state.
9.1.1.3
BYPASS (
‘
b11)
This instruction allows a device to be effectively removed from the scan chain, by inserting a one-
bit shift register stage between TDI and TDO during data shifts. When the instruction is active, the
test logic has no impact upon the system logic performing its system function. When selected, the
shift-register is set to a logic zero on the rising edge of the JTCK during the CAPTURE-DR state.
9.1.1.4
IDCODE (
‘
b10)
This instruction allows the reading of component types via the scan chain. During this instruction,
the 32-bit Device Identification Register (ID-Register) is placed between TDI and TDO. The ID
Register captures a fixed value of (
‘
h 1186B0FD) on the rising edge of JTCK during the
CAPTURE-DR state. The Device Identification Register contains the following information:
Manufacturer ID:
‘
d126; Design Part Number:
‘
d 6251; Design Version Number:
‘
d1.
9.1.2
Boundary Scan Register
The Boundary Scan Register is a 165 bit shift register, made of four styles of shift-register cells
with two sub-types. According to the Boundary Scan Description Language (BSDL):
JTAG_BSRINBOTH,
JTAG_BSROUTBOTH and
JTAG_BSRCTL are designated TYPE2, JTAG_BSRINCLKOBS is designated TYPE1.
Description
Length: 165 BSR cells
JTCK_P Jtag Test Clock
JTDI_P Jtag Test Data Input
JTDO_C Jtag Test Data Output Control enable
JTDO_P Jtag Test Data Output
JTMS_P Jtag Test Mode Select
JTRS_P Jtag Test Reset