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參數(shù)資料
| 型號： | LXT6251A |
| 英文描述： | ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料 |
| 文件頁數(shù)： | 31/76頁 |
| 文件大?。?/td> | 995K |
| 代理商： | LXT6251A |
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21 E1 SDH Mapper
—
LXT6251A
Datasheet
31
received DTBDATA input, if set to
‘
1
’
, the TU time slot data is added from an E1 input port; which
port is determined by the Port Mapping registers. Finally, as with the receive section, the Port
Mapping function is enabled.
It is possible to enable all 21 channels in the Add/Drop mode and use the device in a terminal
configuration. One consequence of this configuration is that both transmit and receive sections
operate with the same clock and timing references.
5.2.1
Data Pass-Through
In the Add/Drop configuration for STM-1, it is necessary to control the pass though of the higher
order overhead bytes and the non-dropped TUG-3 payloads. The LXT6251A uses three external
pins for this control: PTSOH, PTTUGA and PTTUGB.
5.2.1.1
PTSOH
The PTSOH pin controls the pass-through of the SOH and HPOH bytes along with the Telecom
bus timing signals. Connecting this pin high will cause the nine columns of the STM-1 SOH, the
single column of VC-4 HPOH and the two VC-4 fixed stuff columns and the timing signals
MTBJ0J1, MTBPAY, and MTBH4EN to be output on the MTBDATA bus. If PTSOH is tied low,
none of the above mentioned bytes are output: MTBDATA is tri-stated during the corresponding
time slots and timing signal pins are held in tri-state. This pin should be tied low in STM-0 mode as
well as in the STM-1 terminal configuration.
Figure 6. Add/Drop Configuration Data Flow
E1 to VC-12
Mapping
VC-12 to E1
Demapping
Add
Mux
Control
ADD Registers
MUX
PTSOH
PTTUGA
PTTUGB
DTBDATA
DTDx/DTCx
MTDx/MTCx
MTBDATA
Rx
Timing
Tx
Timing
MTBJ0J1
MTBPAYEN
MTBH4EN
DTBJ0J1
DTBPAYEN
DTBH4EN
FF
Control
Receive
Transmit
DTBYCK
MTBYCK
FF
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