參數(shù)資料
型號(hào)： LXT6251A
英文描述： ATM/SONET MAPPER|CMOS|QFP|208PIN|PLASTIC
中文描述： 的ATM / SONET的映射器|的CMOS | QFP封裝| 208PIN |塑料
文件頁數(shù)： 3/76頁
文件大?。?/td> 995K
代理商： LXT6251A
Datasheet
3
21 E1 SDH Mapper — LXT6251A
Contents
1.0
2.0
3.0
Block Diagram
.............................................................................................................7
Pin Assignments and Signal Descriptions
......................................................8
Functional Description
...........................................................................................16
3.1
Introduction..........................................................................................................16
3.2
Receive Section, Terminal Mode ........................................................................16
3.2.1
Receive Alarms......................................................................................17
3.2.1.1 Parity Alarm...............................................................................17
3.2.1.2 Loss of Multiframe.....................................................................17
3.3
High Order Path Adaptation................................................................................18
3.3.1
Alarms and Status..................................................................................18
3.3.1.1 TU-AIS.......................................................................................18
3.3.1.2 TU Loss of Pointer (LOP)..........................................................19
3.4
Low Order Path Termination...............................................................................19
3.4.1
V5 Processing ........................................................................................19
3.4.1.1 BIP-2 Errors (V5, bits 1,2) .........................................................19
3.4.1.2 REI Detection (V5, bit 3)............................................................20
3.4.1.3 RFI Detection (V5, bit 4)............................................................20
3.4.1.4 Signal Label Mismatch (V5, bits 5-7).........................................20
3.4.1.5 Unequipped Detection (V5, bits 5-7) .........................................21
3.4.1.6 VC-AIS Detection (V5, bits 5-7).................................................21
3.4.1.7 RDI Detection (V5, bit 8) ...........................................................21
3.4.2
J2 Processing.........................................................................................21
3.4.2.1 J2 Memory Access....................................................................22
3.4.2.2 CRC-7 Error ..............................................................................22
3.4.2.3 Trace Identifier Mismatch..........................................................23
3.4.3
N2 Processing........................................................................................23
3.4.4
K4 Processing ........................................................................................23
3.4.4.1 Enhanced RDI...........................................................................23
3.4.5
Summary of Alarms causing E1 AIS ......................................................23
3.4.5.1 TU-AIS Alarm ............................................................................24
3.4.5.2 TU-LOP Alarm...........................................................................24
3.4.5.3 Signal Label Mismatch ..............................................................24
3.4.5.4 Unequipped Alarm.....................................................................24
3.4.5.5 J2 Path Label Mismatch............................................................24
3.5
Low Order Path Adaptation.................................................................................24
3.5.1
Desynchronizer ......................................................................................24
Transmit Section, Terminal Mode
.....................................................................26
4.1
Low Order Path Adaptation.................................................................................26
4.2
Low Order Path Termination...............................................................................26
4.2.1
V5 Processing ........................................................................................26
4.2.1.1 BIP-2 .........................................................................................26
4.2.1.2 REI Bit .......................................................................................26
4.2.1.3 RFI Bit .......................................................................................27
4.2.1.4 Signal Label...............................................................................27
4.2.1.5 RDI Bit.......................................................................................27
4.0
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